From 92096685a00414a813aa4735db1706e4e5c6917d Mon Sep 17 00:00:00 2001 From: Ed Tanous Date: Thu, 3 Jul 2025 07:42:46 -0700 Subject: hw/arm/aspeed: Add second SPI chip to Aspeed model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Aspeed2600 has two spi lanes; Add a new struct that can mount the second SPI. Signed-off-by: Ed Tanous Reviewed-by: Cédric Le Goater Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-2-etanous@nvidia.com Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index 973277b..6c36455 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -35,7 +35,9 @@ struct AspeedMachineClass { uint32_t hw_strap2; const char *fmc_model; const char *spi_model; + const char *spi2_model; uint32_t num_cs; + uint32_t num_cs2; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); uint32_t uart_default; -- cgit v1.1