From 56258174238eb25df629a53a96e1ac16a32dc7d4 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 30 Aug 2017 15:21:40 -0300 Subject: hw/ppc: clear pending_events on machine reset The sPAPR machine isn't clearing up the pending events QTAILQ on machine reboot. This allows for unprocessed hotplug/epow events to persist in the queue after reset and, when reasserting the IRQs in check_exception later on, these will be being processed by the OS. This patch implements a new function called 'spapr_clear_pending_events' that clears up the pending_events QTAILQ. This helper is then called inside ppc_spapr_reset to clear up the events queue, preventing old/deprecated events from persisting after a reset. Signed-off-by: Daniel Henrique Barboza Signed-off-by: David Gibson --- include/hw/ppc/spapr.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 2a303a7..5d161ec 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -662,6 +662,7 @@ void spapr_cpu_parse_features(sPAPRMachineState *spapr); int spapr_hpt_shift_for_ramsize(uint64_t ramsize); void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, Error **errp); +void spapr_clear_pending_events(sPAPRMachineState *spapr); /* CPU and LMB DRC release callbacks. */ void spapr_core_release(DeviceState *dev); -- cgit v1.1 From 10f12e6450407b18b4d5a6b50d3852dcfd7fff75 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 30 Aug 2017 15:21:41 -0300 Subject: hw/ppc: CAS reset on early device hotplug This patch is a follow up on the discussions made in patch "hw/ppc: disable hotplug before CAS is completed" that can be found at [1]. At this moment, we do not support CPU/memory hotplug in early boot stages, before CAS. When a hotplug occurs, the event is logged in an internal RTAS event log queue and an IRQ pulse is fired. In regular conditions, the guest handles the interrupt by executing check_exception, fetching the generated hotplug event and enabling the device for use. In early boot, this IRQ isn't caught (SLOF does not handle hotplug events), leaving the event in the rtas event log queue. If the guest executes check_exception due to another hotplug event, the re-assertion of the IRQ ends up de-queuing the first hotplug event as well. In short, a device hotplugged before CAS is considered coldplugged by SLOF. This leads to device misbehavior and, in some cases, guest kernel Ooops when trying to unplug the device. A proper fix would be to turn every device hotplugged before CAS as a colplugged device. This is not trivial to do with the current code base though - the FDT is written in the guest memory at ppc_spapr_reset and can't be retrieved without adding extra state (fdt_size for example) that will need to managed and migrated. Adding the hotplugged DT in the middle of CAS negotiation via the updated DT tree works with CPU devs, but panics the guest kernel at boot. Additional analysis would be necessary for LMBs and PCI devices. There are questions to be made in QEMU/SLOF/kernel level about how we can make this change in a sustainable way. With Linux guests, a fix would be the kernel executing check_exception at boot time, de-queueing the events that happened in early boot and processing them. However, even if/when the newer kernels start fetching these events at boot time, we need to take care of older kernels that won't be doing that. This patch works around the situation by issuing a CAS reset if a hotplugged device is detected during CAS: - the DRC conditions that warrant a CAS reset is the same as those that triggers a DRC migration - the DRC must have a device attached and the DRC state is not equal to its ready_state. With that in mind, this patch makes use of 'spapr_drc_needed' to determine if a CAS reset is needed. - In the middle of CAS negotiations, the function 'spapr_hotplugged_dev_before_cas' goes through all the DRCs to see if there are any DRC that requires a reset, using spapr_drc_needed. If that happens, returns '1' in 'spapr_h_cas_compose_response' which will set spapr->cas_reboot to true, causing the machine to reboot. No changes are made for coldplug devices. [1] http://lists.nongnu.org/archive/html/qemu-devel/2017-08/msg02855.html Signed-off-by: Daniel Henrique Barboza Signed-off-by: David Gibson --- include/hw/ppc/spapr_drc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/ppc/spapr_drc.h b/include/hw/ppc/spapr_drc.h index a7958d0..f8d9f5b 100644 --- a/include/hw/ppc/spapr_drc.h +++ b/include/hw/ppc/spapr_drc.h @@ -257,6 +257,7 @@ int spapr_drc_populate_dt(void *fdt, int fdt_offset, Object *owner, void spapr_drc_attach(sPAPRDRConnector *drc, DeviceState *d, void *fdt, int fdt_start_offset, Error **errp); void spapr_drc_detach(sPAPRDRConnector *drc); +bool spapr_drc_needed(void *opaque); static inline bool spapr_drc_unplug_requested(sPAPRDRConnector *drc) { -- cgit v1.1 From 2e886fb39168942ab03b91062e715946e4af8436 Mon Sep 17 00:00:00 2001 From: Sam Bobroff Date: Wed, 9 Aug 2017 15:38:56 +1000 Subject: ppc: spapr: Make VCPU ID handling private to SPAPR The concept of a VCPU ID that differs from the CPU's index (cpu->cpu_index) exists only within SPAPR machines so, move the functions ppc_get_vcpu_id() and ppc_get_cpu_by_vcpu_id() into spapr.c and rename them appropriately. Signed-off-by: Sam Bobroff Signed-off-by: David Gibson --- include/hw/ppc/spapr.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 5d161ec..91617e3 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -705,4 +705,7 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) +int spapr_vcpu_id(PowerPCCPU *cpu); +PowerPCCPU *spapr_find_cpu(int vcpu_id); + #endif /* HW_SPAPR_H */ -- cgit v1.1 From 517284a77171af6f5676678aea15030ea1887842 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sun, 20 Aug 2017 19:23:05 +0200 Subject: ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs This device appears in other SoCs as well not just in 405 ones Signed-off-by: BALATON Zoltan Reviewed-by: David Gibson Signed-off-by: David Gibson --- include/hw/ppc/ppc4xx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 66e57a5..db50cfa 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -53,6 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, hwaddr *ram_sizes, int do_init); +void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]); + #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" #endif /* PPC4XX_H */ -- cgit v1.1 From 0453428047527ac778489a927b66d591ff3c450c Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sun, 20 Aug 2017 19:23:05 +0200 Subject: ppc4xx: Make MAL emulation more generic Allow MAL with more RX and TX channels as found in newer versions. Signed-off-by: BALATON Zoltan Reviewed-by: David Gibson Signed-off-by: David Gibson --- include/hw/ppc/ppc4xx.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index db50cfa..cb0bb55 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -53,7 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, hwaddr *ram_sizes, int do_init); -void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]); +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, + qemu_irq irqs[4]); #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" -- cgit v1.1 From 3b09bb0fb9bc03f3897da4940ba2fb808c00c038 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sun, 20 Aug 2017 19:23:05 +0200 Subject: ppc4xx_i2c: QOMify Signed-off-by: BALATON Zoltan Signed-off-by: David Gibson --- include/hw/i2c/ppc4xx_i2c.h | 61 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 include/hw/i2c/ppc4xx_i2c.h (limited to 'include') diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h new file mode 100644 index 0000000..e53042f --- /dev/null +++ b/include/hw/i2c/ppc4xx_i2c.h @@ -0,0 +1,61 @@ +/* + * PPC4xx I2C controller emulation + * + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PPC4XX_I2C_H +#define PPC4XX_I2C_H + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/sysbus.h" +#include "hw/i2c/i2c.h" + +#define TYPE_PPC4xx_I2C "ppc4xx-i2c" +#define PPC4xx_I2C(obj) OBJECT_CHECK(PPC4xxI2CState, (obj), TYPE_PPC4xx_I2C) + +typedef struct PPC4xxI2CState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + I2CBus *bus; + qemu_irq irq; + MemoryRegion iomem; + uint8_t mdata; + uint8_t lmadr; + uint8_t hmadr; + uint8_t cntl; + uint8_t mdcntl; + uint8_t sts; + uint8_t extsts; + uint8_t sdata; + uint8_t lsadr; + uint8_t hsadr; + uint8_t clkdiv; + uint8_t intrmsk; + uint8_t xfrcnt; + uint8_t xtcntlss; + uint8_t directcntl; +} PPC4xxI2CState; + +#endif /* PPC4XX_I2C_H */ -- cgit v1.1 From fa98fbfcdfcb980b4a690b8bc93ab597935087b1 Mon Sep 17 00:00:00 2001 From: Sam Bobroff Date: Fri, 18 Aug 2017 15:50:22 +1000 Subject: PPC: KVM: Support machine option to set VSMT mode KVM now allows writing to KVM_CAP_PPC_SMT which has previously been read only. Doing so causes KVM to act, for that VM, as if the host's SMT mode was the given value. This is particularly important on Power 9 systems because their default value is 1, but they are able to support values up to 8. This patch introduces a way to control this capability via a new machine property called VSMT ("Virtual SMT"). If the value is not set on the command line a default is chosen that is, when possible, compatible with legacy systems. Note that the intialization of KVM_CAP_PPC_SMT has changed slightly because it has changed (in KVM) from a global capability to a VM-specific one. This won't cause a problem on older KVMs because VM capabilities fall back to global ones. Signed-off-by: Sam Bobroff Signed-off-by: David Gibson --- include/hw/ppc/spapr.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 91617e3..c1b365f 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -99,6 +99,7 @@ struct sPAPRMachineState { uint64_t rtc_offset; /* Now used only during incoming migration */ struct PPCTimebase tb; bool has_graphics; + uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ Notifier epow_notifier; QTAILQ_HEAD(, sPAPREventLogEntry) pending_events; -- cgit v1.1