From 1cdcfb6e936c25ef470e886ffe86dd46ef36f0f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?In=C3=A8s=20Varhol?= Date: Tue, 5 Mar 2024 22:03:10 +0100 Subject: hw/gpio: Implement STM32L4x5 GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Features supported : - the 8 STM32L4x5 GPIOs are initialized with their reset values (except IDR, see below) - input mode : setting a pin in input mode "externally" (using input irqs) results in an out irq (transmitted to SYSCFG) - output mode : setting a bit in ODR sets the corresponding out irq (if this line is configured in output mode) - pull-up, pull-down - push-pull, open-drain Difference with the real GPIOs : - Alternate Function and Analog mode aren't implemented : pins in AF/Analog behave like pins in input mode - floating pins stay at their last value - register IDR reset values differ from the real one : values are coherent with the other registers reset values and the fact that AF/Analog modes aren't implemented - setting I/O output speed isn't supported - locking port bits isn't supported - ADC function isn't supported - GPIOH has 16 pins instead of 2 pins - writing to registers LCKR, AFRL, AFRH and ASCR is ineffective Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- include/hw/gpio/stm32l4x5_gpio.h | 70 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 include/hw/gpio/stm32l4x5_gpio.h (limited to 'include') diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h new file mode 100644 index 0000000..0d361f3 --- /dev/null +++ b/include/hw/gpio/stm32l4x5_gpio.h @@ -0,0 +1,70 @@ +/* + * STM32L4x5 GPIO (General Purpose Input/Ouput) + * + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 Inès Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +/* + * The reference used is the STMicroElectronics RM0351 Reference manual + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html + */ + +#ifndef HW_STM32L4X5_GPIO_H +#define HW_STM32L4X5_GPIO_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio" +OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO) + +#define GPIO_NUM_PINS 16 + +struct Stm32l4x5GpioState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + /* GPIO registers */ + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t idr; + uint32_t odr; + uint32_t lckr; + uint32_t afrl; + uint32_t afrh; + uint32_t ascr; + + /* GPIO registers reset values */ + uint32_t moder_reset; + uint32_t ospeedr_reset; + uint32_t pupdr_reset; + + /* + * External driving of pins. + * The pins can be set externally through the device + * anonymous input GPIOs lines under certain conditions. + * The pin must not be in push-pull output mode, + * and can't be set high in open-drain mode. + * Pins driven externally and configured to + * output mode will in general be "disconnected" + * (see `get_gpio_pinmask_to_disconnect()`) + */ + uint16_t disconnected_pins; + uint16_t pins_connected_high; + + char *name; + Clock *clk; + qemu_irq pin[GPIO_NUM_PINS]; +}; + +#endif -- cgit v1.1 From 1c38129de8a7f3d62ad2800758d9b2ddfccbdca9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?In=C3=A8s=20Varhol?= Date: Tue, 5 Mar 2024 22:03:11 +0100 Subject: hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell --- include/hw/arm/stm32l4x5_soc.h | 2 ++ include/hw/gpio/stm32l4x5_gpio.h | 1 + include/hw/misc/stm32l4x5_syscfg.h | 3 +-- 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index af67b08..ee5f362 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -30,6 +30,7 @@ #include "hw/misc/stm32l4x5_syscfg.h" #include "hw/misc/stm32l4x5_exti.h" #include "hw/misc/stm32l4x5_rcc.h" +#include "hw/gpio/stm32l4x5_gpio.h" #include "qom/object.h" #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" @@ -49,6 +50,7 @@ struct Stm32l4x5SocState { OrIRQState exti_or_gates[NUM_EXTI_OR_GATES]; Stm32l4x5SyscfgState syscfg; Stm32l4x5RccState rcc; + Stm32l4x5GpioState gpio[NUM_GPIOS]; MemoryRegion sram1; MemoryRegion sram2; diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h index 0d361f3..878bd19 100644 --- a/include/hw/gpio/stm32l4x5_gpio.h +++ b/include/hw/gpio/stm32l4x5_gpio.h @@ -25,6 +25,7 @@ #define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio" OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO) +#define NUM_GPIOS 8 #define GPIO_NUM_PINS 16 struct Stm32l4x5GpioState { diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h index 29c3522..23bb564 100644 --- a/include/hw/misc/stm32l4x5_syscfg.h +++ b/include/hw/misc/stm32l4x5_syscfg.h @@ -26,12 +26,11 @@ #include "hw/sysbus.h" #include "qom/object.h" +#include "hw/gpio/stm32l4x5_gpio.h" #define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg" OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG) -#define NUM_GPIOS 8 -#define GPIO_NUM_PINS 16 #define SYSCFG_NUM_EXTICR 4 struct Stm32l4x5SyscfgState { -- cgit v1.1 From fd7f95f23d6fe485332c1d4b489eb719fcb7c225 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 23 Feb 2024 16:13:00 +0000 Subject: hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016 was unfortunately added with a license of GPL-v3-or-later, which is not compatible with other QEMU code which has a GPL-v2-only license. Relicense the code in the .c and the .h file to GPL-v2-or-later, to make it compatible with the rest of QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Signed-off-by: Paolo Bonzini (for Red Hat) Signed-off-by: Artyom Tarasenko Signed-off-by: Markus Armbruster Signed-off-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Daniel P. Berrangé Acked-by: Alex Bennée Message-id: 20240223161300.938542-1-peter.maydell@linaro.org Signed-off-by: Peter Maydell --- include/hw/rtc/sun4v-rtc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h index fc54dfc..26a9eb6 100644 --- a/include/hw/rtc/sun4v-rtc.h +++ b/include/hw/rtc/sun4v-rtc.h @@ -5,7 +5,7 @@ * * Copyright (c) 2016 Artyom Tarasenko * - * This code is licensed under the GNU GPL v3 or (at your option) any later + * This code is licensed under the GNU GPL v2 or (at your option) any later * version. */ -- cgit v1.1