From dfc973ecc1e8a2c148c0011be89c012891f72384 Mon Sep 17 00:00:00 2001 From: Vitaly Wool Date: Thu, 12 Nov 2020 09:49:51 +0200 Subject: hw/riscv: microchip_pfsoc: add QSPI NOR flash Add QSPI NOR flash definition for Microchip PolarFire SoC. Signed-off-by: Vitaly Wool Acked-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 51d4463..d0c666a 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -97,6 +97,8 @@ enum { MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, MICROCHIP_PFSOC_MMUART4, + MICROCHIP_PFSOC_SPI0, + MICROCHIP_PFSOC_SPI1, MICROCHIP_PFSOC_I2C1, MICROCHIP_PFSOC_GEM0, MICROCHIP_PFSOC_GEM1, @@ -105,6 +107,7 @@ enum { MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, + MICROCHIP_PFSOC_QSPI_XIP, MICROCHIP_PFSOC_IOSCB, MICROCHIP_PFSOC_DRAM_LO, MICROCHIP_PFSOC_DRAM_LO_ALIAS, -- cgit v1.1 From dc4d4aaee31cd3ac4020d3b15729f0a104ce8862 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 16 Dec 2020 10:22:32 -0800 Subject: riscv: spike: Remove target macro conditionals Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com --- include/hw/riscv/spike.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index cddeca2..cdd1a13 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -47,10 +47,4 @@ enum { SPIKE_DRAM }; -#if defined(TARGET_RISCV32) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64 -#endif - #endif -- cgit v1.1 From 09fe17125ec9a2166cf9bef360811dde714b3874 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 16 Dec 2020 10:22:34 -0800 Subject: riscv: virt: Remove target macro conditionals Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com --- include/hw/riscv/virt.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b4ed9a3..84b7a38 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -89,10 +89,4 @@ enum { #define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) -#if defined(TARGET_RISCV32) -#define VIRT_CPU TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -#define VIRT_CPU TYPE_RISCV_CPU_BASE64 -#endif - #endif -- cgit v1.1 From 7893677184681d648165caf9e8a25fccc79b4cf3 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 16 Dec 2020 10:22:37 -0800 Subject: hw/riscv: boot: Remove compile time XLEN checks Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com --- include/hw/riscv/boot.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 0b01988..b6d37a9 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -41,10 +41,12 @@ target_ulong riscv_load_kernel(const char *kernel_filename, hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, - hwaddr rom_size, uint64_t kernel_entry, +void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr, + hwaddr rom_base, hwaddr rom_size, + uint64_t kernel_entry, uint32_t fdt_load_addr, void *fdt); -void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, +void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, + hwaddr rom_size, uint32_t reset_vec_size, uint64_t kernel_entry); -- cgit v1.1 From 3ed2b8ac2dacc22c088ec5793ecde31db2fa0414 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 16 Dec 2020 10:23:08 -0800 Subject: hw/riscv: Use the CPU to determine if 32-bit Instead of using string compares to determine if a RISC-V machine is using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids us having to maintain a list of CPU names to compare against. This commit also fixes the name of the function to match the riscv_cpu_is_32bit() function. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com --- include/hw/riscv/boot.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index b6d37a9..20ff5fe 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -22,10 +22,11 @@ #include "exec/cpu-defs.h" #include "hw/loader.h" +#include "hw/riscv/riscv_hart.h" -bool riscv_is_32_bit(MachineState *machine); +bool riscv_is_32bit(RISCVHartArrayState harts); -target_ulong riscv_calc_kernel_start_addr(MachineState *machine, +target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts, target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, @@ -41,7 +42,8 @@ target_ulong riscv_load_kernel(const char *kernel_filename, hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr, +void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts, + hwaddr saddr, hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, uint32_t fdt_load_addr, void *fdt); -- cgit v1.1 From d31e970a01e7399b9cd43ec0dc00c857d968987e Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 14 Dec 2020 17:56:54 -0800 Subject: riscv/opentitan: Update the OpenTitan memory layout OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com --- include/hw/riscv/opentitan.h | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 5ff0c0f..a5ea3a5 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -55,19 +55,30 @@ enum { IBEX_DEV_UART, IBEX_DEV_GPIO, IBEX_DEV_SPI, - IBEX_DEV_FLASH_CTRL, + IBEX_DEV_I2C, + IBEX_DEV_PATTGEN, IBEX_DEV_RV_TIMER, - IBEX_DEV_AES, - IBEX_DEV_HMAC, - IBEX_DEV_PLIC, + IBEX_DEV_SENSOR_CTRL, + IBEX_DEV_OTP_CTRL, IBEX_DEV_PWRMGR, IBEX_DEV_RSTMGR, IBEX_DEV_CLKMGR, IBEX_DEV_PINMUX, + IBEX_DEV_PADCTRL, + IBEX_DEV_USBDEV, + IBEX_DEV_FLASH_CTRL, + IBEX_DEV_PLIC, + IBEX_DEV_AES, + IBEX_DEV_HMAC, + IBEX_DEV_KMAC, + IBEX_DEV_KEYMGR, + IBEX_DEV_CSRNG, + IBEX_DEV_ENTROPY, + IBEX_DEV_EDNO, + IBEX_DEV_EDN1, IBEX_DEV_ALERT_HANDLER, IBEX_DEV_NMI_GEN, - IBEX_DEV_USBDEV, - IBEX_DEV_PADCTRL, + IBEX_DEV_OTBN, }; enum { -- cgit v1.1