From 9febd175415dbc84e6ff7bda9bf6d90fe060181e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 19 Feb 2021 14:46:05 +0000 Subject: hw/arm/armsse: Add support for SSE variants with a system counter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SSE-300 has a system counter device; add support for SSE variants having this device. As with the existing devices like the cache control block, CPUID block, etc, we don't try to make the MMIO addresses configurable. We can do that if and when we need to model a future SSE variant which has the counter in a different location. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-33-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 104ba8d..149f17d 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -97,6 +97,7 @@ #include "hw/misc/tz-mpc.h" #include "hw/timer/cmsdk-apb-timer.h" #include "hw/timer/cmsdk-apb-dualtimer.h" +#include "hw/timer/sse-counter.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" @@ -164,6 +165,8 @@ struct ARMSSE { CMSDKAPBWatchdog cmsdk_watchdog[3]; + SSECounter sse_counter; + IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; -- cgit v1.1