From 9ee6f678f473007e252934d6acd09c24490d9d42 Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Fri, 10 Feb 2017 12:53:05 +0530 Subject: softfloat: Add round-to-odd rounding mode Power ISA 3.0 introduces a few quadruple precision floating point instructions that support round-to-odd rounding mode. The round-to-odd mode is explained as under: Let Z be the intermediate arithmetic result or the operand of a convert operation. If Z can be represented exactly in the target format, the result is Z. Otherwise the result is either Z1 or Z2 whichever is odd. Here Z1 and Z2 are the next larger and smaller numbers representable in the target format respectively. Signed-off-by: Bharata B Rao Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- include/fpu/softfloat.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 842ec6b..8a39028 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -180,6 +180,8 @@ enum { float_round_up = 2, float_round_to_zero = 3, float_round_ties_away = 4, + /* Not an IEEE rounding mode: round to the closest odd mantissa value */ + float_round_to_odd = 5, }; /*---------------------------------------------------------------------------- -- cgit v1.1