From 9a6d491831e6e12a971f6a0c59e9553e96a9241c Mon Sep 17 00:00:00 2001 From: Francisco Iglesias Date: Fri, 21 Jan 2022 16:11:33 +0000 Subject: hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models Add an orgate and 'or' the interrupts from the BBRAM and RTC models. Signed-off-by: Francisco Iglesias Reviewed-by: Peter Maydell Reviewed-by: Luc Michel Message-id: 20220121161141.14389-3-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 895ba12..62fb6f0 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -85,6 +85,8 @@ struct Versal { XlnxEFuse efuse; XlnxVersalEFuseCtrl efuse_ctrl; XlnxVersalEFuseCache efuse_cache; + + qemu_or_irq apb_irq_orgate; } pmc; struct { @@ -111,8 +113,7 @@ struct Versal { #define VERSAL_GEM1_WAKE_IRQ_0 59 #define VERSAL_ADMA_IRQ_0 60 #define VERSAL_XRAM_IRQ_0 79 -#define VERSAL_BBRAM_APB_IRQ_0 121 -#define VERSAL_RTC_APB_ERR_IRQ 121 +#define VERSAL_PMC_APB_IRQ 121 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_EFUSE_IRQ 139 #define VERSAL_RTC_ALARM_IRQ 142 -- cgit v1.1