From 82a4ed8e5014ee814c63be33987e6783d5eacce2 Mon Sep 17 00:00:00 2001 From: Alexander Wagner Date: Tue, 9 Mar 2021 16:21:30 +0100 Subject: hw/char: disable ibex uart receive if the buffer is full Not disabling the UART leads to QEMU overwriting the UART receive buffer with the newest received byte. The rx_level variable is added to allow the use of the existing OpenTitan driver libraries. Signed-off-by: Alexander Wagner Reviewed-by: Alistair Francis Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de Signed-off-by: Alistair Francis --- include/hw/char/ibex_uart.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/hw/char/ibex_uart.h b/include/hw/char/ibex_uart.h index 03d19e3..546f958 100644 --- a/include/hw/char/ibex_uart.h +++ b/include/hw/char/ibex_uart.h @@ -62,6 +62,8 @@ REG32(FIFO_CTRL, 0x1c) FIELD(FIFO_CTRL, RXILVL, 2, 3) FIELD(FIFO_CTRL, TXILVL, 5, 2) REG32(FIFO_STATUS, 0x20) + FIELD(FIFO_STATUS, TXLVL, 0, 5) + FIELD(FIFO_STATUS, RXLVL, 16, 5) REG32(OVRD, 0x24) REG32(VAL, 0x28) REG32(TIMEOUT_CTRL, 0x2c) @@ -82,6 +84,8 @@ struct IbexUartState { uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE]; uint32_t tx_level; + uint32_t rx_level; + QEMUTimer *fifo_trigger_handle; uint64_t char_tx_time; -- cgit v1.1 From 0489348d0d31f216e925855f3ac37a6fc666aaaf Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Fri, 19 Mar 2021 10:50:40 +1100 Subject: hw/riscv: Add fw_cfg support to virt Provides fw_cfg for the virt machine on riscv. This enables using e.g. ramfb later. Signed-off-by: Asherah Connor Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210318235041.17175-2-ashe@kivikakk.ee Signed-off-by: Alistair Francis --- include/hw/riscv/virt.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 632da52..349fee1 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -40,6 +40,7 @@ struct RISCVVirtState { RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; DeviceState *plic[VIRT_SOCKETS_MAX]; PFlashCFI01 *flash[2]; + FWCfgState *fw_cfg; int fdt_size; }; @@ -53,6 +54,7 @@ enum { VIRT_PLIC, VIRT_UART0, VIRT_VIRTIO, + VIRT_FW_CFG, VIRT_FLASH, VIRT_DRAM, VIRT_PCIE_MMIO, -- cgit v1.1 From d6150ace2bccfee6b5f7bb555ca749739b02f687 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 22 Mar 2021 15:52:47 +0800 Subject: hw/riscv: microchip_pfsoc: Map EMMC/SD mux register Since HSS commit c20a89f8dcac, the Icicle Kit reference design has been updated to use a register mapped at 0x4f000000 instead of a GPIO to control whether eMMC or SD card is to be used. With this support the same HSS image can be used for both eMMC and SD card boot flow, while previously two different board configurations were used. This is undocumented but one can take a look at the HSS code HSS_MMCInit() in services/mmc/mmc_api.c. With this commit, HSS image built from 2020.12 release boots again. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index d0c666a..d30916f 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -109,6 +109,7 @@ enum { MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_QSPI_XIP, MICROCHIP_PFSOC_IOSCB, + MICROCHIP_PFSOC_EMMC_SD_MUX, MICROCHIP_PFSOC_DRAM_LO, MICROCHIP_PFSOC_DRAM_LO_ALIAS, MICROCHIP_PFSOC_DRAM_HI, -- cgit v1.1