From 95b56e173e20267778965a2bfd1afd517f7342c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Tue, 19 Nov 2019 15:11:57 +0100 Subject: aspeed: Add a DRAM memory region at the SoC level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, we link the DRAM memory region to the FMC model (for DMAs) through a property alias at the SoC level. The I2C model will need a similar region for DMA support, add a DRAM region property at the SoC level for both model to use. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Tested-by: Jae Hyun Yoo Signed-off-by: Cédric Le Goater Message-id: 20191119141211.25716-4-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 495c08b..e843809 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -40,6 +40,7 @@ typedef struct AspeedSoCState { ARMCPU cpu[ASPEED_CPUS_NUM]; uint32_t num_cpus; A15MPPrivState a7mpcore; + MemoryRegion *dram_mr; MemoryRegion sram; AspeedVICState vic; AspeedRtcState rtc; -- cgit v1.1