From cdf63440eaaee531e2f5b84a833a707f3825e2ac Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Feb 2019 10:55:15 +0000 Subject: hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit Implement a model of the Message Handling Unit (MHU) found in the Arm SSE-200. This is a simple device which just contains some registers which allow the two cores of the SSE-200 to raise interrupts on each other. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190219125808.25174-2-peter.maydell@linaro.org --- include/hw/misc/armsse-mhu.h | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 include/hw/misc/armsse-mhu.h (limited to 'include') diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h new file mode 100644 index 0000000..e57eafc --- /dev/null +++ b/include/hw/misc/armsse-mhu.h @@ -0,0 +1,44 @@ +/* + * ARM SSE-200 Message Handling Unit (MHU) + * + * Copyright (c) 2019 Linaro Limited + * Written by Peter Maydell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or + * (at your option) any later version. + */ + +/* + * This is a model of the Message Handling Unit (MHU) which is part of the + * Arm SSE-200 and documented in + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * + * QEMU interface: + * + sysbus MMIO region 0: the system information register bank + * + sysbus IRQ 0: interrupt for CPU 0 + * + sysbus IRQ 1: interrupt for CPU 1 + */ + +#ifndef HW_MISC_SSE_MHU_H +#define HW_MISC_SSE_MHU_H + +#include "hw/sysbus.h" + +#define TYPE_ARMSSE_MHU "armsse-mhu" +#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU) + +typedef struct ARMSSEMHU { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq cpu0irq; + qemu_irq cpu1irq; + + uint32_t cpu0intr; + uint32_t cpu1intr; +} ARMSSEMHU; + +#endif -- cgit v1.1 From 68d6b36f7f737485b7c5725a5d746d6302e1cfa1 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Feb 2019 10:55:15 +0000 Subject: hw/arm/armsse: Wire up the MHUs Create and connect the MHUs in the SSE-200. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190219125808.25174-3-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 7ef871c..81e082c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -95,6 +95,7 @@ #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" #include "hw/misc/armsse-cpuid.h" +#include "hw/misc/armsse-mhu.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/core/split-irq.h" @@ -166,7 +167,7 @@ typedef struct ARMSSE { IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; - UnimplementedDeviceState mhu[2]; + ARMSSEMHU mhu[2]; UnimplementedDeviceState ppu[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; -- cgit v1.1 From 394e10d2bb300e4445b0ce37f6d138302f2ff04e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Feb 2019 10:55:16 +0000 Subject: hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name The iotkit-sysctl device has a register it names INITSVRTOR0. This is actually a typo present in the IoTKit documentation and also in part of the SSE-200 documentation: it should be INITSVTOR0 because it is specifying the initial value of the Secure VTOR register in the CPU. Correct the typo. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190219125808.25174-6-peter.maydell@linaro.org --- include/hw/misc/iotkit-sysctl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h index e36613c..17a1455 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -41,7 +41,7 @@ typedef struct IoTKitSysCtl { uint32_t reset_syndrome; uint32_t reset_mask; uint32_t gretreg; - uint32_t initsvrtor0; + uint32_t initsvtor0; uint32_t cpuwait; uint32_t wicctrl; } IoTKitSysCtl; -- cgit v1.1 From 0483641418643d5d4cc4d1328fe7acc4ab36c709 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Feb 2019 10:55:16 +0000 Subject: hw/arm/iotkit-sysctl: Add SSE-200 registers The SYSCTL block in the SSE-200 has some extra registers that are not present in the IoTKit version. Add these registers (as reads-as-written stubs), enabled by a new QOM property. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190219125808.25174-7-peter.maydell@linaro.org --- include/hw/misc/iotkit-sysctl.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'include') diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h index 17a1455..9c2f23e 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -17,6 +17,9 @@ * "system control register" blocks. * * QEMU interface: + * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the + * system information block of the SSE + * (used to identify whether to provide SSE-200-only registers) * + sysbus MMIO region 0: the system information register bank * + sysbus MMIO region 1: the system control register bank */ @@ -44,6 +47,23 @@ typedef struct IoTKitSysCtl { uint32_t initsvtor0; uint32_t cpuwait; uint32_t wicctrl; + uint32_t scsecctrl; + uint32_t fclk_div; + uint32_t sysclk_div; + uint32_t clock_force; + uint32_t initsvtor1; + uint32_t nmi_enable; + uint32_t ewctrl; + uint32_t pdcm_pd_sys_sense; + uint32_t pdcm_pd_sram0_sense; + uint32_t pdcm_pd_sram1_sense; + uint32_t pdcm_pd_sram2_sense; + uint32_t pdcm_pd_sram3_sense; + + /* Properties */ + uint32_t sys_version; + + bool is_sse200; } IoTKitSysCtl; #endif -- cgit v1.1 From aab7a3786f085cb4c6842c3c8ea0c86e2c835248 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Feb 2019 10:55:16 +0000 Subject: hw/arm/armsse: Unify init-svtor and cpuwait handling At the moment the handling of init-svtor and cpuwait initial values is split between armsse.c and iotkit-sysctl.c: the code in armsse.c sets the initial state of the CPU object by setting the init-svtor and start-powered-off properties, but the iotkit-sysctl.c code has its own code setting the reset values of its registers (which are then used when updating the CPU when the guest makes runtime changes). Clean this up by making the armsse.c code set properties on the iotkit-sysctl object to define the initial values of the registers, so they always match the initial CPU state, and update the comments in armsse.c accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190219125808.25174-9-peter.maydell@linaro.org --- include/hw/misc/iotkit-sysctl.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h index 9c2f23e..601c8ec 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -62,6 +62,9 @@ typedef struct IoTKitSysCtl { /* Properties */ uint32_t sys_version; + uint32_t cpuwait_rst; + uint32_t initsvtor0_rst; + uint32_t initsvtor1_rst; bool is_sse200; } IoTKitSysCtl; -- cgit v1.1