From a3d0cf82df353a96848c021805252d63d677d921 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 18 Jan 2024 23:01:43 +1000 Subject: hw/ppc/spapr_hcall: Rename {softmmu -> vhyp_mmu}_resize_hpt_pr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since 'softmmu' is quite a loaded term in QEMU, rename the vhyp MMU facilities to use the vhyp_mmu_ prefix rather than softmmu_. vhyp_mmu_ is chosen because the code that manipulates the hash table via guest software hypercalls is QEMU's implementation of the PAPR hypervisor interface, called vhyp. Reviewed-by: Nicholas Piggin Signed-off-by: Philippe Mathieu-Daudé [npiggin: Pick a different name, explain it in changelog.] Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- include/hw/ppc/spapr.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index e91791a..5b5ba9e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -634,10 +634,13 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, target_ulong *args); -target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, +target_ulong vhyp_mmu_resize_hpt_prepare(PowerPCCPU *cpu, + SpaprMachineState *spapr, target_ulong shift); -target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, - target_ulong flags, target_ulong shift); +target_ulong vhyp_mmu_resize_hpt_commit(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong flags, + target_ulong shift); bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); void push_sregs_to_kvm_pr(SpaprMachineState *spapr); -- cgit v1.1 From 2df5c1f5b014126595a26c6797089d284a3b211c Mon Sep 17 00:00:00 2001 From: Harsh Prateek Bora Date: Wed, 24 Jan 2024 10:30:55 +1000 Subject: ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit spapr_irq_init currently uses existing macro SPAPR_XIRQ_BASE to refer to the range of CPU IPIs during initialization of nr-irqs property. It is more appropriate to have its own define which can be further reused as appropriate for correct interpretation. Suggested-by: Cedric Le Goater Reviewed-by: Cédric Le Goater Tested-by: Kowshik Jois Signed-off-by: Harsh Prateek Bora Signed-off-by: Nicholas Piggin --- include/hw/ppc/spapr_irq.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index c22a72c..4fd2d58 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -14,9 +14,21 @@ #include "qom/object.h" /* - * IRQ range offsets per device type + * The XIVE IRQ backend uses the same layout as the XICS backend but + * covers the full range of the IRQ number space. The IRQ numbers for + * the CPU IPIs are allocated at the bottom of this space, below 4K, + * to preserve compatibility with XICS which does not use that range. + */ + +/* + * CPU IPI range (XIVE only) */ #define SPAPR_IRQ_IPI 0x0 +#define SPAPR_IRQ_NR_IPIS 0x1000 + +/* + * IRQ range offsets per device type + */ #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */ #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000) -- cgit v1.1 From ff557c272c21692e9fa4d5a18e2d8989485b00e4 Mon Sep 17 00:00:00 2001 From: Glenn Miles Date: Mon, 5 Feb 2024 17:40:15 +1000 Subject: misc/pca9552: Let external devices set pca9552 inputs Allow external devices to drive pca9552 input pins by adding input GPIO's to the model. This allows a device to connect its output GPIO's to the pca9552 input GPIO's. In order for an external device to set the state of a pca9552 pin, the pin must first be configured for high impedance (LED is off). If the pca9552 pin is configured to drive the pin low (LED is on), then external input will be ignored. Here is a table describing the logical state of a pca9552 pin given the state being driven by the pca9552 and an external device: PCA9552 Configured State | Hi-Z | Low | ------+------+-----+ External Hi-Z | Hi | Low | Device ------+------+-----+ State Low | Low | Low | ------+------+-----+ Reviewed-by: Andrew Jeffery Signed-off-by: Glenn Miles Signed-off-by: Nicholas Piggin --- include/hw/misc/pca9552.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h index b6f4e26..c36525f 100644 --- a/include/hw/misc/pca9552.h +++ b/include/hw/misc/pca9552.h @@ -30,7 +30,8 @@ struct PCA955xState { uint8_t pointer; uint8_t regs[PCA955X_NR_REGS]; - qemu_irq gpio[PCA955X_PIN_COUNT_MAX]; + qemu_irq gpio_out[PCA955X_PIN_COUNT_MAX]; + uint8_t ext_state[PCA955X_PIN_COUNT_MAX]; char *description; /* For debugging purpose only */ }; -- cgit v1.1 From 33467ecb86e7938df605d0384a3a0e3e8a57c707 Mon Sep 17 00:00:00 2001 From: Glenn Miles Date: Mon, 5 Feb 2024 17:40:16 +1000 Subject: ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Power Hypervisor code expects to see a pca9552 device connected to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left- justified address of 0xC6). This is used by hypervisor code to control PCIe slot power during hotplug events. Reviewed-by: Cédric Le Goater Signed-off-by: Glenn Miles Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7e5fef7..110ac9a 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -76,6 +76,7 @@ struct PnvMachineClass { int compat_size; void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); + void (*i2c_init)(PnvMachineState *pnv); }; struct PnvMachineState { -- cgit v1.1 From de0c7d543bcaf4cbde936668817f610bbd18e897 Mon Sep 17 00:00:00 2001 From: Glenn Miles Date: Mon, 5 Feb 2024 17:40:16 +1000 Subject: misc: Add a pca9554 GPIO device model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specs are available here: https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf This is a simple model supporting the basic registers for GPIO mode. The device also supports an interrupt output line but the model does not yet support this. Reviewed-by: Cédric Le Goater Signed-off-by: Glenn Miles Signed-off-by: Nicholas Piggin --- include/hw/misc/pca9554.h | 36 ++++++++++++++++++++++++++++++++++++ include/hw/misc/pca9554_regs.h | 19 +++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 include/hw/misc/pca9554.h create mode 100644 include/hw/misc/pca9554_regs.h (limited to 'include') diff --git a/include/hw/misc/pca9554.h b/include/hw/misc/pca9554.h new file mode 100644 index 0000000..54bfc4c --- /dev/null +++ b/include/hw/misc/pca9554.h @@ -0,0 +1,36 @@ +/* + * PCA9554 I/O port + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef PCA9554_H +#define PCA9554_H + +#include "hw/i2c/i2c.h" +#include "qom/object.h" + +#define TYPE_PCA9554 "pca9554" +typedef struct PCA9554State PCA9554State; +DECLARE_INSTANCE_CHECKER(PCA9554State, PCA9554, + TYPE_PCA9554) + +#define PCA9554_NR_REGS 4 +#define PCA9554_PIN_COUNT 8 + +struct PCA9554State { + /*< private >*/ + I2CSlave i2c; + /*< public >*/ + + uint8_t len; + uint8_t pointer; + + uint8_t regs[PCA9554_NR_REGS]; + qemu_irq gpio_out[PCA9554_PIN_COUNT]; + uint8_t ext_state[PCA9554_PIN_COUNT]; + char *description; /* For debugging purpose only */ +}; + +#endif diff --git a/include/hw/misc/pca9554_regs.h b/include/hw/misc/pca9554_regs.h new file mode 100644 index 0000000..602c4a9 --- /dev/null +++ b/include/hw/misc/pca9554_regs.h @@ -0,0 +1,19 @@ +/* + * PCA9554 I/O port registers + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef PCA9554_REGS_H +#define PCA9554_REGS_H + +/* + * Bits [0:1] are used to address a specific register. + */ +#define PCA9554_INPUT 0 /* read only input register */ +#define PCA9554_OUTPUT 1 /* read/write pin output state */ +#define PCA9554_POLARITY 2 /* Set polarity of input register */ +#define PCA9554_CONFIG 3 /* Set pins as inputs our ouputs */ + +#endif -- cgit v1.1 From 4d2cd2d8697164927620fe31f46f4a67e86c4f5f Mon Sep 17 00:00:00 2001 From: Glenn Miles Date: Mon, 5 Feb 2024 17:40:17 +1000 Subject: ppc/pnv: Test pnv i2c master and connected devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tests the following for both P9 and P10: - I2C master POR status - I2C master status after immediate reset Tests the following for powernv10-ranier only: - Config pca9552 hotplug device pins as inputs then Read the INPUT0/1 registers to verify all pins are high - Connected GPIO pin tests of P10 PCA9552 device. Tests output of pins 0-4 affect input of pins 5-9 respectively. - PCA9554 GPIO pins test. Tests input and ouput functionality. Reviewed-by: Cédric Le Goater Signed-off-by: Glenn Miles Signed-off-by: Nicholas Piggin --- include/hw/i2c/pnv_i2c_regs.h | 143 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 include/hw/i2c/pnv_i2c_regs.h (limited to 'include') diff --git a/include/hw/i2c/pnv_i2c_regs.h b/include/hw/i2c/pnv_i2c_regs.h new file mode 100644 index 0000000..85e96ff --- /dev/null +++ b/include/hw/i2c/pnv_i2c_regs.h @@ -0,0 +1,143 @@ +/* + * PowerNV I2C Controller Register Definitions + * + * Copyright (c) 2024, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PNV_I2C_REGS_H +#define PNV_I2C_REGS_H + +/* I2C FIFO register */ +#define I2C_FIFO_REG 0x4 +#define I2C_FIFO PPC_BITMASK(0, 7) + +/* I2C command register */ +#define I2C_CMD_REG 0x5 +#define I2C_CMD_WITH_START PPC_BIT(0) +#define I2C_CMD_WITH_ADDR PPC_BIT(1) +#define I2C_CMD_READ_CONT PPC_BIT(2) +#define I2C_CMD_WITH_STOP PPC_BIT(3) +#define I2C_CMD_INTR_STEERING PPC_BITMASK(6, 7) /* P9 */ +#define I2C_CMD_INTR_STEER_HOST 1 +#define I2C_CMD_INTR_STEER_OCC 2 +#define I2C_CMD_DEV_ADDR PPC_BITMASK(8, 14) +#define I2C_CMD_READ_NOT_WRITE PPC_BIT(15) +#define I2C_CMD_LEN_BYTES PPC_BITMASK(16, 31) +#define I2C_MAX_TFR_LEN 0xfff0ull + +/* I2C mode register */ +#define I2C_MODE_REG 0x6 +#define I2C_MODE_BIT_RATE_DIV PPC_BITMASK(0, 15) +#define I2C_MODE_PORT_NUM PPC_BITMASK(16, 21) +#define I2C_MODE_ENHANCED PPC_BIT(28) +#define I2C_MODE_DIAGNOSTIC PPC_BIT(29) +#define I2C_MODE_PACING_ALLOW PPC_BIT(30) +#define I2C_MODE_WRAP PPC_BIT(31) + +/* I2C watermark register */ +#define I2C_WATERMARK_REG 0x7 +#define I2C_WATERMARK_HIGH PPC_BITMASK(16, 19) +#define I2C_WATERMARK_LOW PPC_BITMASK(24, 27) + +/* + * I2C interrupt mask and condition registers + * + * NB: The function of 0x9 and 0xa changes depending on whether you're reading + * or writing to them. When read they return the interrupt condition bits + * and on writes they update the interrupt mask register. + * + * The bit definitions are the same for all the interrupt registers. + */ +#define I2C_INTR_MASK_REG 0x8 + +#define I2C_INTR_RAW_COND_REG 0x9 /* read */ +#define I2C_INTR_MASK_OR_REG 0x9 /* write*/ + +#define I2C_INTR_COND_REG 0xa /* read */ +#define I2C_INTR_MASK_AND_REG 0xa /* write */ + +#define I2C_INTR_ALL PPC_BITMASK(16, 31) +#define I2C_INTR_INVALID_CMD PPC_BIT(16) +#define I2C_INTR_LBUS_PARITY_ERR PPC_BIT(17) +#define I2C_INTR_BKEND_OVERRUN_ERR PPC_BIT(18) +#define I2C_INTR_BKEND_ACCESS_ERR PPC_BIT(19) +#define I2C_INTR_ARBT_LOST_ERR PPC_BIT(20) +#define I2C_INTR_NACK_RCVD_ERR PPC_BIT(21) +#define I2C_INTR_DATA_REQ PPC_BIT(22) +#define I2C_INTR_CMD_COMP PPC_BIT(23) +#define I2C_INTR_STOP_ERR PPC_BIT(24) +#define I2C_INTR_I2C_BUSY PPC_BIT(25) +#define I2C_INTR_NOT_I2C_BUSY PPC_BIT(26) +#define I2C_INTR_SCL_EQ_1 PPC_BIT(28) +#define I2C_INTR_SCL_EQ_0 PPC_BIT(29) +#define I2C_INTR_SDA_EQ_1 PPC_BIT(30) +#define I2C_INTR_SDA_EQ_0 PPC_BIT(31) + +/* I2C status register */ +#define I2C_RESET_I2C_REG 0xb /* write */ +#define I2C_RESET_ERRORS 0xc +#define I2C_STAT_REG 0xb /* read */ +#define I2C_STAT_INVALID_CMD PPC_BIT(0) +#define I2C_STAT_LBUS_PARITY_ERR PPC_BIT(1) +#define I2C_STAT_BKEND_OVERRUN_ERR PPC_BIT(2) +#define I2C_STAT_BKEND_ACCESS_ERR PPC_BIT(3) +#define I2C_STAT_ARBT_LOST_ERR PPC_BIT(4) +#define I2C_STAT_NACK_RCVD_ERR PPC_BIT(5) +#define I2C_STAT_DATA_REQ PPC_BIT(6) +#define I2C_STAT_CMD_COMP PPC_BIT(7) +#define I2C_STAT_STOP_ERR PPC_BIT(8) +#define I2C_STAT_UPPER_THRS PPC_BITMASK(9, 15) +#define I2C_STAT_ANY_I2C_INTR PPC_BIT(16) +#define I2C_STAT_PORT_HISTORY_BUSY PPC_BIT(19) +#define I2C_STAT_SCL_INPUT_LEVEL PPC_BIT(20) +#define I2C_STAT_SDA_INPUT_LEVEL PPC_BIT(21) +#define I2C_STAT_PORT_BUSY PPC_BIT(22) +#define I2C_STAT_INTERFACE_BUSY PPC_BIT(23) +#define I2C_STAT_FIFO_ENTRY_COUNT PPC_BITMASK(24, 31) + +#define I2C_STAT_ANY_ERR (I2C_STAT_INVALID_CMD | I2C_STAT_LBUS_PARITY_ERR | \ + I2C_STAT_BKEND_OVERRUN_ERR | \ + I2C_STAT_BKEND_ACCESS_ERR | I2C_STAT_ARBT_LOST_ERR | \ + I2C_STAT_NACK_RCVD_ERR | I2C_STAT_STOP_ERR) + + +#define I2C_INTR_ACTIVE \ + ((I2C_STAT_ANY_ERR >> 16) | I2C_INTR_CMD_COMP | I2C_INTR_DATA_REQ) + +/* Pseudo-status used for timeouts */ +#define I2C_STAT_PSEUDO_TIMEOUT PPC_BIT(63) + +/* I2C extended status register */ +#define I2C_EXTD_STAT_REG 0xc +#define I2C_EXTD_STAT_FIFO_SIZE PPC_BITMASK(0, 7) +#define I2C_EXTD_STAT_MSM_CURSTATE PPC_BITMASK(11, 15) +#define I2C_EXTD_STAT_SCL_IN_SYNC PPC_BIT(16) +#define I2C_EXTD_STAT_SDA_IN_SYNC PPC_BIT(17) +#define I2C_EXTD_STAT_S_SCL PPC_BIT(18) +#define I2C_EXTD_STAT_S_SDA PPC_BIT(19) +#define I2C_EXTD_STAT_M_SCL PPC_BIT(20) +#define I2C_EXTD_STAT_M_SDA PPC_BIT(21) +#define I2C_EXTD_STAT_HIGH_WATER PPC_BIT(22) +#define I2C_EXTD_STAT_LOW_WATER PPC_BIT(23) +#define I2C_EXTD_STAT_I2C_BUSY PPC_BIT(24) +#define I2C_EXTD_STAT_SELF_BUSY PPC_BIT(25) +#define I2C_EXTD_STAT_I2C_VERSION PPC_BITMASK(27, 31) + +/* I2C residual front end/back end length */ +#define I2C_RESIDUAL_LEN_REG 0xd +#define I2C_RESIDUAL_FRONT_END PPC_BITMASK(0, 15) +#define I2C_RESIDUAL_BACK_END PPC_BITMASK(16, 31) + +/* Port busy register */ +#define I2C_PORT_BUSY_REG 0xe +#define I2C_SET_S_SCL_REG 0xd +#define I2C_RESET_S_SCL_REG 0xf +#define I2C_SET_S_SDA_REG 0x10 +#define I2C_RESET_S_SDA_REG 0x11 + +#define PNV_I2C_FIFO_SIZE 8 +#define PNV_I2C_MAX_BUSSES 64 + +#endif /* PNV_I2C_REGS_H */ -- cgit v1.1 From 1adf24708bf7f8506fab6f2d53530af0210e6658 Mon Sep 17 00:00:00 2001 From: Chalapathi V Date: Tue, 23 Jan 2024 16:37:01 +1000 Subject: hw/ppc: Add pnv nest pervasive common chiplet model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with chiplet-specific registers. All nest chiplets have a common basic set of registers and This model will provide the registers functionality for common registers of nest chiplet (Pervasive Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets) This commit implement the read/write functions of chiplet control registers. Reviewed-by: Cédric Le Goater Signed-off-by: Chalapathi V Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_nest_pervasive.h | 32 ++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_xscom.h | 3 +++ 2 files changed, 35 insertions(+) create mode 100644 include/hw/ppc/pnv_nest_pervasive.h (limited to 'include') diff --git a/include/hw/ppc/pnv_nest_pervasive.h b/include/hw/ppc/pnv_nest_pervasive.h new file mode 100644 index 0000000..73cacf3 --- /dev/null +++ b/include/hw/ppc/pnv_nest_pervasive.h @@ -0,0 +1,32 @@ +/* + * QEMU PowerPC nest pervasive common chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PPC_PNV_NEST_CHIPLET_PERVASIVE_H +#define PPC_PNV_NEST_CHIPLET_PERVASIVE_H + +#define TYPE_PNV_NEST_CHIPLET_PERVASIVE "pnv-nest-chiplet-pervasive" +#define PNV_NEST_CHIPLET_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj), TYPE_PNV_NEST_CHIPLET_PERVASIVE) + +typedef struct PnvPervasiveCtrlRegs { +#define PNV_CPLT_CTRL_SIZE 6 + uint64_t cplt_ctrl[PNV_CPLT_CTRL_SIZE]; + uint64_t cplt_cfg0; + uint64_t cplt_cfg1; + uint64_t cplt_stat0; + uint64_t cplt_mask0; + uint64_t ctrl_protect_mode; + uint64_t ctrl_atomic_lock; +} PnvPervasiveCtrlRegs; + +typedef struct PnvNestChipletPervasive { + DeviceState parent; + MemoryRegion xscom_ctrl_regs_mr; + PnvPervasiveCtrlRegs control_regs; +} PnvNestChipletPervasive; + +#endif /*PPC_PNV_NEST_CHIPLET_PERVASIVE_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index f5becba..3e15706 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -170,6 +170,9 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_XIVE2_BASE 0x2010800 #define PNV10_XSCOM_XIVE2_SIZE 0x400 +#define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000 +#define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400 + #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ #define PNV10_XSCOM_PEC_NEST_SIZE 0x100 -- cgit v1.1 From 5706b0064d6a78c32bf46f18910bc4e10dde2687 Mon Sep 17 00:00:00 2001 From: Chalapathi V Date: Tue, 23 Jan 2024 16:37:02 +1000 Subject: hw/ppc: Add N1 chiplet model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The N1 chiplet handle the high speed i/o traffic over PCIe and others. The N1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a N1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. This commit also implement the read/write method for the powerbus scom registers Reviewed-by: Cédric Le Goater Signed-off-by: Chalapathi V Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_n1_chiplet.h | 32 ++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_xscom.h | 6 ++++++ 2 files changed, 38 insertions(+) create mode 100644 include/hw/ppc/pnv_n1_chiplet.h (limited to 'include') diff --git a/include/hw/ppc/pnv_n1_chiplet.h b/include/hw/ppc/pnv_n1_chiplet.h new file mode 100644 index 0000000..a7ad039 --- /dev/null +++ b/include/hw/ppc/pnv_n1_chiplet.h @@ -0,0 +1,32 @@ +/* + * QEMU PowerPC N1 chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PPC_PNV_N1_CHIPLET_H +#define PPC_PNV_N1_CHIPLET_H + +#include "hw/ppc/pnv_nest_pervasive.h" + +#define TYPE_PNV_N1_CHIPLET "pnv-N1-chiplet" +#define PNV_N1_CHIPLET(obj) OBJECT_CHECK(PnvN1Chiplet, (obj), TYPE_PNV_N1_CHIPLET) + +typedef struct PnvPbScom { + uint64_t mode; + uint64_t hp_mode2_curr; +} PnvPbScom; + +typedef struct PnvN1Chiplet { + DeviceState parent; + MemoryRegion xscom_pb_eq_mr; + MemoryRegion xscom_pb_es_mr; + PnvNestChipletPervasive nest_pervasive; /* common pervasive chiplet unit */ +#define PNV_PB_SCOM_EQ_SIZE 8 + PnvPbScom eq[PNV_PB_SCOM_EQ_SIZE]; +#define PNV_PB_SCOM_ES_SIZE 4 + PnvPbScom es[PNV_PB_SCOM_ES_SIZE]; +} PnvN1Chiplet; +#endif /*PPC_PNV_N1_CHIPLET_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 3e15706..535ae1d 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -173,6 +173,12 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000 #define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400 +#define PNV10_XSCOM_N1_PB_SCOM_EQ_BASE 0x3011000 +#define PNV10_XSCOM_N1_PB_SCOM_EQ_SIZE 0x200 + +#define PNV10_XSCOM_N1_PB_SCOM_ES_BASE 0x3011300 +#define PNV10_XSCOM_N1_PB_SCOM_ES_SIZE 0x100 + #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ #define PNV10_XSCOM_PEC_NEST_SIZE 0x100 -- cgit v1.1 From c295d3b0907ce40d45d9068d875f91363db4c194 Mon Sep 17 00:00:00 2001 From: Chalapathi V Date: Tue, 23 Jan 2024 16:37:02 +1000 Subject: hw/ppc: N1 chiplet wiring MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This part of the patchset connects the nest1 chiplet model to p10 chip. Reviewed-by: Cédric Le Goater Signed-off-by: Chalapathi V Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_chip.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 0ab5c42..9b06c8d 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -4,6 +4,7 @@ #include "hw/pci-host/pnv_phb4.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_n1_chiplet.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_psi.h" @@ -113,6 +114,7 @@ struct Pnv10Chip { PnvOCC occ; PnvSBE sbe; PnvHomer homer; + PnvN1Chiplet n1_chiplet; uint32_t nr_quads; PnvQuad *quads; -- cgit v1.1 From 9a69950feb0983cde8a97f8c7d1623e81b912412 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Thu, 11 Aug 2022 22:08:34 +1000 Subject: ppc/pnv: Add POWER9/10 chiptod model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ChipTOD (for Time-Of-Day) is a chip pervasive facility in IBM POWER (powernv) processors that keeps a time of day clock. In particular for this model are facilities that initialise and start the time of day clock, and that synchronise that clock to cores on the chip, and to other chips. In this way, all cores on all chips can synchronise timebase (TB). This model implements functionality sufficient to run the skiboot chiptod synchronisation procedure (with the following core timebase state machine implementation). It does not modify the TB in the cores where the real hardware would, because the QEMU ppc timebase implementation is always synchronised acros all cores. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_chiptod.h | 49 ++++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_xscom.h | 9 ++++++++ 2 files changed, 58 insertions(+) create mode 100644 include/hw/ppc/pnv_chiptod.h (limited to 'include') diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h new file mode 100644 index 0000000..ca77052 --- /dev/null +++ b/include/hw/ppc/pnv_chiptod.h @@ -0,0 +1,49 @@ +/* + * QEMU PowerPC PowerNV Emulation of some CHIPTOD behaviour + * + * Copyright (c) 2022-2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PPC_PNV_CHIPTOD_H +#define PPC_PNV_CHIPTOD_H + +#include "qom/object.h" + +#define TYPE_PNV_CHIPTOD "pnv-chiptod" +OBJECT_DECLARE_TYPE(PnvChipTOD, PnvChipTODClass, PNV_CHIPTOD) +#define TYPE_PNV9_CHIPTOD TYPE_PNV_CHIPTOD "-POWER9" +DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV9_CHIPTOD, TYPE_PNV9_CHIPTOD) +#define TYPE_PNV10_CHIPTOD TYPE_PNV_CHIPTOD "-POWER10" +DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV10_CHIPTOD, TYPE_PNV10_CHIPTOD) + +enum tod_state { + tod_error = 0, + tod_not_set = 7, + tod_running = 2, + tod_stopped = 1, +}; + +struct PnvChipTOD { + DeviceState xd; + + PnvChip *chip; + MemoryRegion xscom_regs; + + bool primary; + bool secondary; + enum tod_state tod_state; + uint64_t tod_error; + uint64_t pss_mss_ctrl_reg; +}; + +struct PnvChipTODClass { + DeviceClass parent_class; + + void (*broadcast_ttype)(PnvChipTOD *sender, uint32_t trigger); + + int xscom_size; +}; + +#endif /* PPC_PNV_CHIPTOD_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 535ae1d..6209e18 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -64,6 +64,9 @@ struct PnvXScomInterfaceClass { #define PNV_XSCOM_PSIHB_BASE 0x2010900 #define PNV_XSCOM_PSIHB_SIZE 0x20 +#define PNV_XSCOM_CHIPTOD_BASE 0x0040000 +#define PNV_XSCOM_CHIPTOD_SIZE 0x31 + #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 @@ -93,6 +96,9 @@ struct PnvXScomInterfaceClass { #define PNV9_XSCOM_I2CM_BASE 0xa0000 #define PNV9_XSCOM_I2CM_SIZE 0x1000 +#define PNV9_XSCOM_CHIPTOD_BASE PNV_XSCOM_CHIPTOD_BASE +#define PNV9_XSCOM_CHIPTOD_SIZE PNV_XSCOM_CHIPTOD_SIZE + #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE #define PNV9_XSCOM_OCC_SIZE 0x8000 @@ -155,6 +161,9 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_I2CM_BASE PNV9_XSCOM_I2CM_BASE #define PNV10_XSCOM_I2CM_SIZE PNV9_XSCOM_I2CM_SIZE +#define PNV10_XSCOM_CHIPTOD_BASE PNV9_XSCOM_CHIPTOD_BASE +#define PNV10_XSCOM_CHIPTOD_SIZE PNV9_XSCOM_CHIPTOD_SIZE + #define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE #define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE -- cgit v1.1 From de3ba0cc38ffb96265f29c2399df0a5c0f301f40 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Mon, 27 Nov 2023 17:44:24 +1000 Subject: ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wire the ChipTOD model to powernv9 and powernv10 machines. Suggested-by-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv_chip.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 9b06c8d..af4cd7a 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -2,6 +2,7 @@ #define PPC_PNV_CHIP_H #include "hw/pci-host/pnv_phb4.h" +#include "hw/ppc/pnv_chiptod.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" #include "hw/ppc/pnv_n1_chiplet.h" @@ -79,6 +80,7 @@ struct Pnv9Chip { PnvXive xive; Pnv9Psi psi; PnvLpcController lpc; + PnvChipTOD chiptod; PnvOCC occ; PnvSBE sbe; PnvHomer homer; @@ -111,6 +113,7 @@ struct Pnv10Chip { PnvXive2 xive; Pnv9Psi psi; PnvLpcController lpc; + PnvChipTOD chiptod; PnvOCC occ; PnvSBE sbe; PnvHomer homer; -- cgit v1.1 From cde2ba34a951997f01c184acf6e3a29eb6a81e79 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Thu, 23 Nov 2023 18:02:36 +1000 Subject: ppc/pnv: Implement the ChipTOD to Core transfer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One of the functions of the ChipTOD is to transfer TOD to the Core (aka PC - Pervasive Core) timebase facility. The ChipTOD can be programmed with a target address to send the TOD value to. The hardware implementation seems to perform this by sending the TOD value to a SCOM address. This implementation grabs the core directly and manipulates the timebase facility state in the core. This is a hack, but it works enough for now. A better implementation would implement the transfer to the PnvCore xscom register and drive the timebase state machine from there. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- include/hw/ppc/pnv.h | 2 ++ include/hw/ppc/pnv_chiptod.h | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 110ac9a..476b136 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -28,6 +28,7 @@ #define TYPE_PNV_CHIP "pnv-chip" +typedef struct PnvCore PnvCore; typedef struct PnvChip PnvChip; typedef struct Pnv8Chip Pnv8Chip; typedef struct Pnv9Chip Pnv9Chip; @@ -56,6 +57,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, TYPE_PNV_CHIP_POWER10) +PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id); PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); typedef struct PnvPHB PnvPHB; diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h index ca77052..fde569b 100644 --- a/include/hw/ppc/pnv_chiptod.h +++ b/include/hw/ppc/pnv_chiptod.h @@ -25,6 +25,8 @@ enum tod_state { tod_stopped = 1, }; +typedef struct PnvCore PnvCore; + struct PnvChipTOD { DeviceState xd; @@ -36,12 +38,14 @@ struct PnvChipTOD { enum tod_state tod_state; uint64_t tod_error; uint64_t pss_mss_ctrl_reg; + PnvCore *slave_pc_target; }; struct PnvChipTODClass { DeviceClass parent_class; void (*broadcast_ttype)(PnvChipTOD *sender, uint32_t trigger); + PnvCore *(*tx_ttype_target)(PnvChipTOD *chiptod, uint64_t val); int xscom_size; }; -- cgit v1.1