From bbb02509f2fece730350620a429276143a1e2232 Mon Sep 17 00:00:00 2001 From: Vitaly Cheptsov Date: Thu, 25 May 2023 10:37:48 +0100 Subject: fsl-imx6: Add SNVS support for i.MX6 boards SNVS is supported on both i.MX6 and i.MX6UL and is needed to support shutdown on the board. Cc: Peter Maydell (odd fixer:SABRELITE / i.MX6) Cc: Jean-Christophe Dubois (reviewer:SABRELITE / i.MX6) Cc: qemu-arm@nongnu.org (open list:SABRELITE / i.MX6) Cc: qemu-devel@nongnu.org (open list:All patches CC here) Signed-off-by: Vitaly Cheptsov Message-id: 20230515095015.66860-1-cheptsov@ispras.ru Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 8329145..5b4d48d 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -21,6 +21,7 @@ #include "hw/cpu/a9mpcore.h" #include "hw/misc/imx6_ccm.h" #include "hw/misc/imx6_src.h" +#include "hw/misc/imx7_snvs.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/char/imx_serial.h" #include "hw/timer/imx_gpt.h" @@ -59,6 +60,7 @@ struct FslIMX6State { A9MPPrivState a9mpcore; IMX6CCMState ccm; IMX6SRCState src; + IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX6_NUM_UARTS]; IMXGPTState gpt; IMXEPITState epit[FSL_IMX6_NUM_EPITS]; -- cgit v1.1 From 3b736c61849ebc16776143a947a90a731b0aea55 Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:49 +0100 Subject: hw/arm/smmuv3: Update translation config to hold stage-2 In preparation for adding stage-2 support, add a S2 config struct(SMMUS2Cfg), composed of the following fields and embedded in the main SMMUTransCfg: -tsz: Size of IPA input region (S2T0SZ) -sl0: Start level of translation (S2SL0) -affd: AF Fault Disable (S2AFFD) -record_faults: Record fault events (S2R) -granule_sz: Granule page shift (based on S2TG) -vmid: Virtual Machine ID (S2VMID) -vttb: Address of translation table base (S2TTB) -eff_ps: Effective PA output range (based on S2PS) They will be used in the next patches in stage-2 address translation. The fields in SMMUS2Cfg, are reordered to make the shared and stage-1 fields next to each other, this reordering didn't change the struct size (104 bytes before and after). Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas. oas is stage-1 output address size. However, it is used to check input address in case stage-1 is unimplemented or bypassed according to SMMUv3 manual IHI0070.E "3.4. Address sizes" Shared fields: stage, disabled, bypassed, aborted, iotlb_*. No functional change intended. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-3-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 9fcff26..9cf3f37 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -58,25 +58,41 @@ typedef struct SMMUTLBEntry { uint8_t granule; } SMMUTLBEntry; +/* Stage-2 configuration. */ +typedef struct SMMUS2Cfg { + uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ + uint8_t sl0; /* Start level of translation (S2SL0) */ + bool affd; /* AF Fault Disable (S2AFFD) */ + bool record_faults; /* Record fault events (S2R) */ + uint8_t granule_sz; /* Granule page shift (based on S2TG) */ + uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ + uint16_t vmid; /* Virtual Machine ID (S2VMID) */ + uint64_t vttb; /* Address of translation table base (S2TTB) */ +} SMMUS2Cfg; + /* * Generic structure populated by derived SMMU devices * after decoding the configuration information and used as * input to the page table walk */ typedef struct SMMUTransCfg { + /* Shared fields between stage-1 and stage-2. */ int stage; /* translation stage */ - bool aa64; /* arch64 or aarch32 translation table */ bool disabled; /* smmu is disabled */ bool bypassed; /* translation is bypassed */ bool aborted; /* translation is aborted */ + uint32_t iotlb_hits; /* counts IOTLB hits */ + uint32_t iotlb_misses; /* counts IOTLB misses*/ + /* Used by stage-1 only. */ + bool aa64; /* arch64 or aarch32 translation table */ bool record_faults; /* record fault events */ uint64_t ttb; /* TT base address */ uint8_t oas; /* output address width */ uint8_t tbi; /* Top Byte Ignore */ uint16_t asid; SMMUTransTableInfo tt[2]; - uint32_t iotlb_hits; /* counts IOTLB hits for this asid */ - uint32_t iotlb_misses; /* counts IOTLB misses for this asid */ + /* Used by stage-2 only. */ + struct SMMUS2Cfg s2cfg; } SMMUTransCfg; typedef struct SMMUDevice { -- cgit v1.1 From bcc919e756cd793e59038f59ad69d543b369f689 Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:49 +0100 Subject: hw/arm/smmuv3: Refactor stage-1 PTW In preparation for adding stage-2 support, rename smmu_ptw_64 to smmu_ptw_64_s1 and refactor some of the code so it can be reused in stage-2 page table walk. Remove AA64 check from PTW as decode_cd already ensures that AA64 is used, otherwise it faults with C_BAD_CD. A stage member is added to SMMUPTWEventInfo to differentiate between stage-1 and stage-2 ptw faults. Add stage argument to trace_smmu_ptw_level be consistent with other trace events. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-4-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 9cf3f37..97cea8e 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -23,9 +23,18 @@ #include "hw/pci/pci.h" #include "qom/object.h" -#define SMMU_PCI_BUS_MAX 256 -#define SMMU_PCI_DEVFN_MAX 256 -#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) +#define SMMU_PCI_BUS_MAX 256 +#define SMMU_PCI_DEVFN_MAX 256 +#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) + +/* VMSAv8-64 Translation constants and functions */ +#define VMSA_LEVELS 4 + +#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) +#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ + (VMSA_LEVELS - (lvl))) +#define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ + VMSA_BIT_LVL(isz, strd, lvl)) - 1) /* * Page table walk error types @@ -40,6 +49,7 @@ typedef enum { } SMMUPTWEventType; typedef struct SMMUPTWEventInfo { + int stage; SMMUPTWEventType type; dma_addr_t addr; /* fetched address that induced an abort, if any */ } SMMUPTWEventInfo; -- cgit v1.1 From 21eb5b5cde7f6f75751837d3082ce8b36070af33 Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:50 +0100 Subject: hw/arm/smmuv3: Parse STE config for stage-2 Parse stage-2 configuration from STE and populate it in SMMUS2Cfg. Validity of field values are checked when possible. Only AA64 tables are supported and Small Translation Tables (STT) are not supported. According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields with an S2 prefix (with the exception of S2VMID) are IGNORED when stage-2 bypasses translation (Config[1] == 0). Which means that VMID can be used(for TLB tagging) even if stage-2 is bypassed, so we parse it unconditionally when S2P exists. Otherwise it is set to -1.(only S1P) As stall is not supported, if S2S is set the translation would abort. For S2R, we reuse the same code used for stage-1 with flag record_faults. However when nested translation is supported we would need to separate stage-1 and stage-2 faults. Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S. Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Reviewed-by: Eric Auger Message-id: 20230516203327.2051088-6-smostafa@google.com [PMM: fixed format string] Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 1 + include/hw/arm/smmuv3.h | 3 +++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 97cea8e..4f1405d 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -29,6 +29,7 @@ /* VMSAv8-64 Translation constants and functions */ #define VMSA_LEVELS 4 +#define VMSA_MAX_S2_CONCAT 16 #define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) #define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index a0c0264..6031d7d 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -83,4 +83,7 @@ struct SMMUv3Class { #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) +#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P) +#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P) + #endif -- cgit v1.1 From 2eaeb7d593254a34f3e551865b687886c2698f96 Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:50 +0100 Subject: hw/arm/smmuv3: Add VMID to TLB tagging Allow TLB to be tagged with VMID. If stage-1 is only supported, VMID is set to -1 and ignored from STE and CMD_TLBI_NH* cmds. Update smmu_iotlb_insert trace event to have vmid. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-8-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 4f1405d..3cbb499 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -125,6 +125,7 @@ typedef struct SMMUPciBus { typedef struct SMMUIOTLBKey { uint64_t iova; uint16_t asid; + uint16_t vmid; uint8_t tg; uint8_t level; } SMMUIOTLBKey; @@ -188,11 +189,11 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, +void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); /* Unmap the range of all the notifiers registered to any IOMMU mr */ -- cgit v1.1 From ccc3ee38713381a823a6b9229b36a0a1b36d919d Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:51 +0100 Subject: hw/arm/smmuv3: Add CMDs related to stage-2 CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the same as CMD_TLBI_NH_VAA. CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID. For stage-1 only commands, add a check to throw CERROR_ILL if used when stage-1 is not supported. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-9-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 3cbb499..fd8d772 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -193,6 +193,7 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); +void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); -- cgit v1.1 From 8cefcc3b7127f1c497aa832378fe69453fb9db2c Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:51 +0100 Subject: hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 As everything is in place, we can use a new system property to advertise which stage is supported and remove bad_ste from STE stage2 config. The property added arm-smmuv3.stage can have 3 values: - "1": Stage-1 only is advertised. - "2": Stage-2 only is advertised. If not passed or an unsupported value is passed, it will default to stage-1. Advertise VMID16. Don't try to decode CD, if stage-2 is configured. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-11-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmuv3.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 6031d7d..d183a62 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -62,6 +62,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; + char *stage; }; typedef enum { -- cgit v1.1 From 5d6c687c9d2249de3f41d8d71baa1f15cc5cf112 Mon Sep 17 00:00:00 2001 From: Enze Li Date: Thu, 25 May 2023 14:43:45 +0800 Subject: Update copyright dates to 2023 I noticed that in the latest version, the copyright string is still 2022, even though 2023 is halfway through. This patch fixes that and fixes the documentation along with it. Signed-off-by: Enze Li Reviewed-by: Peter Maydell Message-id: 20230525064345.1152801-1-lienze@kylinos.cn Signed-off-by: Peter Maydell --- include/qemu/help-texts.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/qemu/help-texts.h b/include/qemu/help-texts.h index 4f265fe..d0359f8 100644 --- a/include/qemu/help-texts.h +++ b/include/qemu/help-texts.h @@ -2,7 +2,7 @@ #define QEMU_HELP_TEXTS_H /* Copyright string for -version arguments, About dialogs, etc */ -#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \ +#define QEMU_COPYRIGHT "Copyright (c) 2003-2023 " \ "Fabrice Bellard and the QEMU Project developers" /* Bug reporting information for --help arguments, About dialogs, etc */ -- cgit v1.1