From f14d65e8992499a179ecdf1901137ce496a0a607 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 30 Jul 2019 16:35:21 -0700 Subject: riscv: plic: Remove unused interrupt functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alistair Francis Reviewed-by: Jonathan Behrens Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Chih-Min Chao Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_plic.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index b0edba2..4421e81 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -69,9 +69,6 @@ typedef struct SiFivePLICState { uint32_t aperture_size; } SiFivePLICState; -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq); -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq); - DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, -- cgit v1.1 From 751f8f41331951077f3fc17dd245c23b5a18b595 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 16 Aug 2019 06:09:35 -0700 Subject: riscv: Add a helper routine for finding firmware This adds a helper routine for finding firmware. It is currently used only for "-bios default" case. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/boot.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 1f21c2b..66075d0 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -25,6 +25,7 @@ void riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr); +char *riscv_find_firmware(const char *firmware_filename); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr); target_ulong riscv_load_kernel(const char *kernel_filename); -- cgit v1.1 From 9a2551ed6f946e96cd54ea3f3499d785a1f27c3d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 5 Sep 2019 08:55:16 -0700 Subject: riscv: sifive_test: Add reset functionality This adds a reset opcode for sifive_test device to trigger a system reset for testing purpose. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_test.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h index 3a603a6..1ec416a 100644 --- a/include/hw/riscv/sifive_test.h +++ b/include/hw/riscv/sifive_test.h @@ -36,7 +36,8 @@ typedef struct SiFiveTestState { enum { FINISHER_FAIL = 0x3333, - FINISHER_PASS = 0x5555 + FINISHER_PASS = 0x5555, + FINISHER_RESET = 0x7777 }; DeviceState *sifive_test_create(hwaddr addr); -- cgit v1.1 From 56449d20e937e807e4fc35fa3e5a38f7636e7046 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:19:58 -0700 Subject: riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_e_prci.h | 69 ++++++++++++++++++++++++++++++++++++++ include/hw/riscv/sifive_prci.h | 71 ---------------------------------------- 2 files changed, 69 insertions(+), 71 deletions(-) create mode 100644 include/hw/riscv/sifive_e_prci.h delete mode 100644 include/hw/riscv/sifive_prci.h (limited to 'include') diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h new file mode 100644 index 0000000..c4b76aa --- /dev/null +++ b/include/hw/riscv/sifive_e_prci.h @@ -0,0 +1,69 @@ +/* + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_E_PRCI_H +#define HW_SIFIVE_E_PRCI_H + +enum { + SIFIVE_E_PRCI_HFROSCCFG = 0x0, + SIFIVE_E_PRCI_HFXOSCCFG = 0x4, + SIFIVE_E_PRCI_PLLCFG = 0x8, + SIFIVE_E_PRCI_PLLOUTDIV = 0xC +}; + +enum { + SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31), + SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30) +}; + +enum { + SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31), + SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30) +}; + +enum { + SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16), + SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17), + SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18), + SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31) +}; + +enum { + SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) +}; + +#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" + +#define SIFIVE_E_PRCI(obj) \ + OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI) + +typedef struct SiFiveEPRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t hfrosccfg; + uint32_t hfxosccfg; + uint32_t pllcfg; + uint32_t plloutdiv; +} SiFiveEPRCIState; + +DeviceState *sifive_e_prci_create(hwaddr addr); + +#endif diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h deleted file mode 100644 index 8b7de13..0000000 --- a/include/hw/riscv/sifive_prci.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface - * - * Copyright (c) 2017 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#ifndef HW_SIFIVE_PRCI_H -#define HW_SIFIVE_PRCI_H - -#include "hw/sysbus.h" - -enum { - SIFIVE_PRCI_HFROSCCFG = 0x0, - SIFIVE_PRCI_HFXOSCCFG = 0x4, - SIFIVE_PRCI_PLLCFG = 0x8, - SIFIVE_PRCI_PLLOUTDIV = 0xC -}; - -enum { - SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31), - SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30) -}; - -enum { - SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31), - SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30) -}; - -enum { - SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16), - SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17), - SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18), - SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31) -}; - -enum { - SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) -}; - -#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" - -#define SIFIVE_PRCI(obj) \ - OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) - -typedef struct SiFivePRCIState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - MemoryRegion mmio; - uint32_t hfrosccfg; - uint32_t hfxosccfg; - uint32_t pllcfg; - uint32_t plloutdiv; -} SiFivePRCIState; - -DeviceState *sifive_prci_create(hwaddr addr); - -#endif -- cgit v1.1 From d0730344fd8f27ce5e98efd43efe594ae3a00087 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:00 -0700 Subject: riscv: sifive_e: prci: Update the PRCI register block size Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_e_prci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h index c4b76aa..698b0b4 100644 --- a/include/hw/riscv/sifive_e_prci.h +++ b/include/hw/riscv/sifive_e_prci.h @@ -47,6 +47,8 @@ enum { SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) }; +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 + #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" #define SIFIVE_E_PRCI(obj) \ -- cgit v1.1 From 20f41c869830fdf0ac9aec8d14b766167f47ce7d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:02 -0700 Subject: riscv: Add a sifive_cpu.h to include both E and U cpu type defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_cpu.h | 31 +++++++++++++++++++++++++++++++ include/hw/riscv/sifive_e.h | 7 +------ include/hw/riscv/sifive_u.h | 7 +------ 3 files changed, 33 insertions(+), 12 deletions(-) create mode 100644 include/hw/riscv/sifive_cpu.h (limited to 'include') diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h new file mode 100644 index 0000000..1367996 --- /dev/null +++ b/include/hw/riscv/sifive_cpu.h @@ -0,0 +1,31 @@ +/* + * SiFive CPU types + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_CPU_H +#define HW_SIFIVE_CPU_H + +#if defined(TARGET_RISCV32) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 +#elif defined(TARGET_RISCV64) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#endif + +#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 9c868dd..25ce7aa 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -20,6 +20,7 @@ #define HW_SIFIVE_E_H #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" @@ -84,10 +85,4 @@ enum { #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#endif - #endif diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be021ce..f25bad8 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -21,6 +21,7 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_cpu.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -78,10 +79,4 @@ enum { #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - #endif -- cgit v1.1 From e8c56787cd78f5d26285120f85bf898f5d3693b9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:04 -0700 Subject: riscv: hart: Add a "hartid-base" property to RISC-V hart array At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/riscv_hart.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 3b52b50..c75856f 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState { /*< public >*/ uint32_t num_harts; + uint32_t hartid_base; char *cpu_type; RISCVCPU *harts; } RISCVHartArrayState; -- cgit v1.1 From f3d47d580402d11b73108de807031124c135e370 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:05 -0700 Subject: riscv: sifive_u: Set the minimum number of cpus to 2 It is not useful if we only have one management CPU. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis [Palmer: Set default CPUs to 2] Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index f25bad8..6d22741 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -69,6 +69,8 @@ enum { SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; +#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 + #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 -- cgit v1.1 From ecdfe393b69985eb90ac4921287439dc47ed35b4 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:06 -0700 Subject: riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 6d22741..6b2b5b6 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -32,7 +32,10 @@ typedef struct SiFiveUSoCState { SysBusDevice parent_obj; /*< public >*/ - RISCVHartArrayState cpus; + CPUClusterState e_cluster; + CPUClusterState u_cluster; + RISCVHartArrayState e_cpus; + RISCVHartArrayState u_cpus; DeviceState *plic; CadenceGEMState gem; } SiFiveUSoCState; @@ -70,6 +73,7 @@ enum { }; #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 +#define SIFIVE_U_COMPUTE_CPU_COUNT 4 #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 54 -- cgit v1.1 From 0d95299468c8f19a306b93bb9b6940ea55945db5 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:08 -0700 Subject: riscv: sifive: Implement PRCI model for FU540 This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u_prci.h | 81 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 include/hw/riscv/sifive_u_prci.h (limited to 'include') diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h new file mode 100644 index 0000000..60a2eab --- /dev/null +++ b/include/hw/riscv/sifive_u_prci.h @@ -0,0 +1,81 @@ +/* + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_U_PRCI_H +#define HW_SIFIVE_U_PRCI_H + +#define SIFIVE_U_PRCI_HFXOSCCFG 0x00 +#define SIFIVE_U_PRCI_COREPLLCFG0 0x04 +#define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C +#define SIFIVE_U_PRCI_DDRPLLCFG1 0x10 +#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C +#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20 +#define SIFIVE_U_PRCI_CORECLKSEL 0x24 +#define SIFIVE_U_PRCI_DEVICESRESET 0x28 +#define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C + +/* + * Current FU540-C000 manual says ready bit is at bit 29, but + * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31. + * We have to trust the actual code that works. + * + * see https://github.com/sifive/freedom-u540-c000-bootloader + */ + +#define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30) +#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31) + +/* xxxPLLCFG0 register bits */ +#define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0) +#define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6) +#define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15) +#define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25) +#define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31) + +/* xxxPLLCFG1 register bits */ +#define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24) + +/* coreclksel register bits */ +#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0) + + +#define SIFIVE_U_PRCI_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci" + +#define SIFIVE_U_PRCI(obj) \ + OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI) + +typedef struct SiFiveUPRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t hfxosccfg; + uint32_t corepllcfg0; + uint32_t ddrpllcfg0; + uint32_t ddrpllcfg1; + uint32_t gemgxlpllcfg0; + uint32_t gemgxlpllcfg1; + uint32_t coreclksel; + uint32_t devicesreset; + uint32_t clkmuxstatus; +} SiFiveUPRCIState; + +#endif /* HW_SIFIVE_U_PRCI_H */ -- cgit v1.1 From e1724d09a6dc090063cad9d88d9994b9f55f5716 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:09 -0700 Subject: riscv: sifive_u: Generate hfclk and rtcclk nodes To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 6b2b5b6..2441814 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -69,6 +69,8 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_HFCLK_FREQ = 33333333, + SIFIVE_U_RTCCLK_FREQ = 1000000, SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; -- cgit v1.1 From af14c840418bee1b22e5b1bc403dcc8c69492517 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:10 -0700 Subject: riscv: sifive_u: Add PRCI block to the SoC Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2441814..bb46745 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -22,6 +22,7 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" +#include "hw/riscv/sifive_u_prci.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -37,6 +38,7 @@ typedef struct SiFiveUSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + SiFiveUPRCIState prci; CadenceGEMState gem; } SiFiveUSoCState; @@ -55,6 +57,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_PLIC, + SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_DRAM, -- cgit v1.1 From 806c64b7b0e782b7f1414478486c67df718a0f00 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:11 -0700 Subject: riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u_prci.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h index 60a2eab..0a531fd 100644 --- a/include/hw/riscv/sifive_u_prci.h +++ b/include/hw/riscv/sifive_u_prci.h @@ -78,4 +78,14 @@ typedef struct SiFiveUPRCIState { uint32_t clkmuxstatus; } SiFiveUPRCIState; +/* + * Clock indexes for use by Device Tree data and the PRCI driver. + * + * These values are from sifive-fu540-prci.h in the Linux kernel. + */ +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + #endif /* HW_SIFIVE_U_PRCI_H */ -- cgit v1.1 From 4b55bc2b5f7ff065da5d2b813ee5153c598d3764 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:12 -0700 Subject: riscv: sifive_u: Update UART base addresses and IRQs This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index bb46745..7dfd1cb 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -65,8 +65,8 @@ enum { }; enum { - SIFIVE_U_UART0_IRQ = 3, - SIFIVE_U_UART1_IRQ = 4, + SIFIVE_U_UART0_IRQ = 4, + SIFIVE_U_UART1_IRQ = 5, SIFIVE_U_GEM_IRQ = 0x35 }; -- cgit v1.1 From 9fb45c62ae88726eb472656ae90683098473041a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:15 -0700 Subject: riscv: sifive: Implement a model for SiFive FU540 OTP This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u_otp.h | 80 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 include/hw/riscv/sifive_u_otp.h (limited to 'include') diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000..6392975 --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,80 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +#define SIFIVE_U_OTP_PA 0x00 +#define SIFIVE_U_OTP_PAIO 0x04 +#define SIFIVE_U_OTP_PAS 0x08 +#define SIFIVE_U_OTP_PCE 0x0C +#define SIFIVE_U_OTP_PCLK 0x10 +#define SIFIVE_U_OTP_PDIN 0x14 +#define SIFIVE_U_OTP_PDOUT 0x18 +#define SIFIVE_U_OTP_PDSTB 0x1C +#define SIFIVE_U_OTP_PPROG 0x20 +#define SIFIVE_U_OTP_PTC 0x24 +#define SIFIVE_U_OTP_PTM 0x28 +#define SIFIVE_U_OTP_PTM_REP 0x2C +#define SIFIVE_U_OTP_PTR 0x30 +#define SIFIVE_U_OTP_PTRIM 0x34 +#define SIFIVE_U_OTP_PWE 0x38 + +#define SIFIVE_U_OTP_PCE_EN (1 << 0) + +#define SIFIVE_U_OTP_PDSTB_EN (1 << 0) + +#define SIFIVE_U_OTP_PTRIM_EN (1 << 0) + +#define SIFIVE_U_OTP_PA_MASK 0xfff +#define SIFIVE_U_OTP_NUM_FUSES 0x1000 +#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveUOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveUOTPState; + +#endif /* HW_SIFIVE_U_OTP_H */ -- cgit v1.1 From 5461c4fefed627eac9e1cadfb5754fc985d6df89 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:16 -0700 Subject: riscv: sifive_u: Instantiate OTP memory with a serial number This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 7dfd1cb..4d4733c 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -23,6 +23,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_u_prci.h" +#include "hw/riscv/sifive_u_otp.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -39,6 +40,7 @@ typedef struct SiFiveUSoCState { RISCVHartArrayState u_cpus; DeviceState *plic; SiFiveUPRCIState prci; + SiFiveUOTPState otp; CadenceGEMState gem; } SiFiveUSoCState; @@ -60,6 +62,7 @@ enum { SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_OTP, SIFIVE_U_DRAM, SIFIVE_U_GEM }; -- cgit v1.1 From 7b6bb66f02bc81a6bb5d90a4fe08ab9c6841a936 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:17 -0700 Subject: riscv: sifive_u: Fix broken GEM support At present the GEM support in sifive_u machine is seriously broken. The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000Mbps link speed changes, that is mapped to 0x100a0000. We can simply map it into MMIO space without special handling using create_unimplemented_device(). Update the GEM node compatible string to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 4d4733c..5270851 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -64,7 +64,8 @@ enum { SIFIVE_U_UART1, SIFIVE_U_OTP, SIFIVE_U_DRAM, - SIFIVE_U_GEM + SIFIVE_U_GEM, + SIFIVE_U_GEM_MGMT }; enum { -- cgit v1.1 From 81e94379f75c40b77d577c6bff2d7e23c9904ccf Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Sep 2019 09:20:18 -0700 Subject: riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_u.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 5270851..e4df298 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -77,8 +77,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_HFCLK_FREQ = 33333333, - SIFIVE_U_RTCCLK_FREQ = 1000000, - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 + SIFIVE_U_RTCCLK_FREQ = 1000000 }; #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 -- cgit v1.1