From 600b819f235d6b6eb33fc33e09fe64f53eb9a9a6 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 9 May 2021 17:16:14 +0200 Subject: accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Forward tlb_flush_page_bits_by_mmuidx_all_cpus to tlb_flush_range_by_mmuidx_all_cpus passing TARGET_PAGE_SIZE. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-id: 20210509151618.2331764-6-f4bug@amsat.org Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5a5f6d4..9a3dbb7 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -276,6 +276,12 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, target_ulong len, uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, + target_ulong len, uint16_t idxmap, + unsigned bits); + /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for @@ -384,6 +390,13 @@ static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, unsigned bits) { } +static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, + target_ulong addr, + target_ulong len, + uint16_t idxmap, + unsigned bits) +{ +} #endif /** * probe_access: -- cgit v1.1