From 5bddf92e689c0a3da57f4fd17b83d4eb1e436b80 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 4 May 2021 13:09:11 +0100 Subject: hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some boards, SCC config register CFG0 bit 0 controls whether parts of the board memory map are remapped. Support this with: * a device property scc-cfg0 so the board can specify the initial value of the CFG0 register * an outbound GPIO line which tracks bit 0 and which the board can wire up to provide the remapping Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210504120912.23094-3-peter.maydell@linaro.org --- include/hw/misc/mps2-scc.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index ea261ea..3b2d13a 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -18,8 +18,14 @@ * + QOM property "scc-cfg4": value of the read-only CFG4 register * + QOM property "scc-aid": value of the read-only SCC_AID register * + QOM property "scc-id": value of the read-only SCC_ID register + * + QOM property "scc-cfg0": reset value of the CFG0 register * + QOM property array "oscclk": reset values of the OSCCLK registers * (which are accessed via the SYS_CFG channel provided by this device) + * + named GPIO output "remap": this tracks the value of CFG0 register + * bit 0. Boards where this bit controls memory remapping should + * connect this GPIO line to a function performing that mapping. + * Boards where bit 0 has no special function should leave the GPIO + * output disconnected. */ #ifndef MPS2_SCC_H #define MPS2_SCC_H @@ -55,6 +61,9 @@ struct MPS2SCC { uint32_t num_oscclk; uint32_t *oscclk; uint32_t *oscclk_reset; + uint32_t cfg0_reset; + + qemu_irq remap; }; #endif -- cgit v1.1