From 4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 11 Apr 2017 17:29:59 +0200 Subject: ppc/pnv: Add support for POWER8+ LPC Controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It adds the Naples chip which supports proper LPC interrupts via the LPC controller rather than via an external CPLD. Signed-off-by: Benjamin Herrenschmidt [clg: - updated for qemu-2.9 - ported on latest PowerNV patchset - moved the IRQ handler in pnv_lpc.c - introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ] Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- include/hw/ppc/pnv_lpc.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 38e5506..ccf969af 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -23,6 +23,8 @@ #define PNV_LPC(obj) \ OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC) +typedef struct PnvPsi PnvPsi; + typedef struct PnvLpcController { DeviceState parent; @@ -62,6 +64,12 @@ typedef struct PnvLpcController { /* XSCOM registers */ MemoryRegion xscom_regs; + + /* PSI to generate interrupts */ + PnvPsi *psi; } PnvLpcController; +qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, + int nirqs); + #endif /* _PPC_PNV_LPC_H */ -- cgit v1.1