From 4b50b8d9f2bdc007d632a6d0781de1126c5d9c76 Mon Sep 17 00:00:00 2001 From: Michael Clark Date: Sat, 3 Mar 2018 01:31:12 +1300 Subject: RISC-V HART Array Holds the state of a heterogenous array of RISC-V hardware threads. Reviewed-by: Richard Henderson Signed-off-by: Sagar Karandikar Signed-off-by: Michael Clark --- include/hw/riscv/riscv_hart.h | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 include/hw/riscv/riscv_hart.h (limited to 'include') diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h new file mode 100644 index 0000000..0671d88 --- /dev/null +++ b/include/hw/riscv/riscv_hart.h @@ -0,0 +1,39 @@ +/* + * QEMU RISC-V Hart Array interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * Holds the state of a heterogenous array of RISC-V harts + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef HW_RISCV_HART_H +#define HW_RISCV_HART_H + +#define TYPE_RISCV_HART_ARRAY "riscv.hart_array" + +#define RISCV_HART_ARRAY(obj) \ + OBJECT_CHECK(RISCVHartArrayState, (obj), TYPE_RISCV_HART_ARRAY) + +typedef struct RISCVHartArrayState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + uint32_t num_harts; + char *cpu_type; + RISCVCPU *harts; +} RISCVHartArrayState; + +#endif -- cgit v1.1