From 3ca109c3f8d6225efdfa801252d25f3e526b004a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sat, 16 Nov 2019 07:08:50 -0800 Subject: riscv/sifive_u: Add a serial property to the sifive_u machine At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com> [ Changed by AF: - Use the SoC's serial property to pass the info to the SoC - Fixup commit title - Rebase on file restructuring ] Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_u.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a2baa1d..16c297e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -61,6 +61,7 @@ typedef struct SiFiveUState { int fdt_size; bool start_in_flash; + uint32_t serial; } SiFiveUState; enum { -- cgit v1.1