From 97175c3f096d2f3be2b90ae09d9c0205719bc791 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Mon, 25 Mar 2019 02:03:47 -0700 Subject: hw/registerfields.h: Add 8bit and 16bit register macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some RX peripheral use 8bit and 16bit registers. Add the 8bit and 16bit APIs. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-4-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/registerfields.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'include') diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58..0407edb 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -22,6 +22,14 @@ enum { A_ ## reg = (addr) }; \ enum { R_ ## reg = (addr) / 4 }; +#define REG8(reg, addr) \ + enum { A_ ## reg = (addr) }; \ + enum { R_ ## reg = (addr) }; + +#define REG16(reg, addr) \ + enum { A_ ## reg = (addr) }; \ + enum { R_ ## reg = (addr) / 2 }; + /* Define SHIFT, LENGTH and MASK constants for a field within a register */ /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH @@ -34,6 +42,12 @@ MAKE_64BIT_MASK(shift, length)}; /* Extract a field from a register */ +#define FIELD_EX8(storage, reg, field) \ + extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX16(storage, reg, field) \ + extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) @@ -49,6 +63,22 @@ * Assigning values larger then the target field will result in * compilation warnings. */ +#define FIELD_DP8(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v = { .v = val }; \ + uint8_t d; \ + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) +#define FIELD_DP16(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v = { .v = val }; \ + uint16_t d; \ + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) #define FIELD_DP32(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ -- cgit v1.1 From 4aea3d0c5148f7983f6032ca418081fbe36625e4 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Mon, 21 Jan 2019 05:17:38 -0800 Subject: target/rx: RX disassembler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-8-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/disas/dis-asm.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index f87f468..c5f9fa0 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -226,6 +226,10 @@ enum bfd_architecture #define bfd_mach_nios2r2 2 bfd_arch_lm32, /* Lattice Mico32 */ #define bfd_mach_lm32 1 + bfd_arch_rx, /* Renesas RX */ +#define bfd_mach_rx 0x75 +#define bfd_mach_rx_v2 0x76 +#define bfd_mach_rx_v3 0x77 bfd_arch_last }; #define bfd_mach_s390_31 31 @@ -436,6 +440,7 @@ int print_insn_little_nios2 (bfd_vma, disassemble_info*); int print_insn_xtensa (bfd_vma, disassemble_info*); int print_insn_riscv32 (bfd_vma, disassemble_info*); int print_insn_riscv64 (bfd_vma, disassemble_info*); +int print_insn_rx(bfd_vma, disassemble_info *); #if 0 /* Fetch the disassembler for a given BFD, if that support is available. */ -- cgit v1.1 From c8c35e5f51c4d54bced7aa05fbd8e2371e493182 Mon Sep 17 00:00:00 2001 From: Yoshinori Sato Date: Mon, 21 Jan 2019 05:18:59 -0800 Subject: Add rx-softmmu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson [PMD: Squashed patches from Richard Henderson modifying qapi/common.json and tests/machine-none-test.c] Message-Id: <20200224141923.82118-21-ysato@users.sourceforge.jp> [PMD: Added @since 5.0 tag in SysEmuTarget] Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/exec/poison.h | 1 + include/sysemu/arch_init.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/exec/poison.h b/include/exec/poison.h index 955eb86..7b9ac36 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -26,6 +26,7 @@ #pragma GCC poison TARGET_PPC #pragma GCC poison TARGET_PPC64 #pragma GCC poison TARGET_ABI32 +#pragma GCC poison TARGET_RX #pragma GCC poison TARGET_S390X #pragma GCC poison TARGET_SH4 #pragma GCC poison TARGET_SPARC diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 01392dc..71a7a28 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -24,6 +24,7 @@ enum { QEMU_ARCH_NIOS2 = (1 << 17), QEMU_ARCH_HPPA = (1 << 18), QEMU_ARCH_RISCV = (1 << 19), + QEMU_ARCH_RX = (1 << 20), QEMU_ARCH_NONE = (1 << 31), }; -- cgit v1.1