From ebe31c0a8ef7b59fd96171fe694339ce69ee24a6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Thu, 16 Aug 2018 14:05:29 +0100 Subject: aspeed: add a max_ram_size property to the memory controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will be used to construct a memory region beyond the RAM region to let firmwares scan the address space with load/store to guess how much RAM the SoC has. Signed-off-by: Cédric Le Goater Signed-off-by: Joel Stanley Tested-by: Cédric Le Goater Message-id: 20180807075757.7242-7-joel@jms.id.au Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/misc/aspeed_sdmc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw') diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index e079c66..b3c926a 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -27,6 +27,7 @@ typedef struct AspeedSDMCState { uint32_t silicon_rev; uint32_t ram_bits; uint64_t ram_size; + uint64_t max_ram_size; uint32_t fixed_conf; } AspeedSDMCState; -- cgit v1.1