From c4e1f0b48322a9bc98c37f8413553cb6131daafe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 4 Sep 2019 09:05:01 +0200 Subject: aspeed/smc: Add support for DMAs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FMC controller on the Aspeed SoCs support DMA to access the flash modules. It can operate in a normal mode, to copy to or from the flash module mapping window, or in a checksum calculation mode, to evaluate the best clock settings for reads. The model introduces two custom address spaces for DMAs: one for the AHB window of the FMC flash devices and one for the DRAM. The latter is populated using a "dram" link set from the machine with the RAM container region. Signed-off-by: Cédric Le Goater Acked-by: Joel Stanley Message-id: 20190904070506.1052-6-clg@kaod.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/ssi/aspeed_smc.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/hw') diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index aa07dac..32ce691 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -46,6 +46,8 @@ typedef struct AspeedSMCController { hwaddr flash_window_base; uint32_t flash_window_size; bool has_dma; + hwaddr dma_flash_mask; + hwaddr dma_dram_mask; uint32_t nregs; } AspeedSMCController; @@ -101,6 +103,10 @@ typedef struct AspeedSMCState { /* for DMA support */ uint64_t sdram_base; + AddressSpace flash_as; + MemoryRegion *dram_mr; + AddressSpace dram_as; + AspeedSMCFlash *flashes; uint8_t snoop_index; -- cgit v1.1