From a9d477c4e3d614409a48d12f34624c2dd9f1ec2d Mon Sep 17 00:00:00 2001 From: Christoffer Dall Date: Mon, 18 Nov 2013 19:26:33 -0800 Subject: arm_gic: Add GICC_APRn state to the GICState The GICC_APRn registers are not currently supported by the ARM GIC v2.0 emulation. This patch adds the missing state. Note that we also change the number of APRs to use a define GIC_NR_APRS based on the maximum number of preemption levels. This patch also adds RAZ/WI accessors for the four registers on the emulated CPU interface. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall Signed-off-by: Peter Maydell --- include/hw/intc/arm_gic_common.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include/hw') diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 983c3cf..89384c2 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -31,6 +31,9 @@ /* Maximum number of possible CPU interfaces, determined by GIC architecture */ #define GIC_NCPU 8 +#define MAX_NR_GROUP_PRIO 128 +#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) + typedef struct gic_irq_state { /* The enable bits are only banked for per-cpu interrupts. */ uint8_t enabled; @@ -75,6 +78,22 @@ typedef struct GICState { uint8_t bpr[GIC_NCPU]; uint8_t abpr[GIC_NCPU]; + /* The APR is implementation defined, so we choose a layout identical to + * the KVM ABI layout for QEMU's implementation of the gic: + * If an interrupt for preemption level X is active, then + * APRn[X mod 32] == 0b1, where n = X / 32 + * otherwise the bit is clear. + * + * TODO: rewrite the interrupt acknowlege/complete routines to use + * the APR registers to track the necessary information to update + * s->running_priority[] on interrupt completion (ie completely remove + * last_active[][] and running_irq[]). This will be necessary if we ever + * want to support TCG<->KVM migration, or TCG guests which can + * do power management involving powering down and restarting + * the GIC. + */ + uint32_t apr[GIC_NR_APRS][GIC_NCPU]; + uint32_t num_cpu; MemoryRegion iomem; /* Distributor */ -- cgit v1.1