From d177892d4a48668a422772e19bed9b6baa384a08 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sat, 1 May 2021 10:03:51 +0200 Subject: aspeed/smc: Remove unused "sdram-base" property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Philippe Mathieu-Daudé Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210407171637.777743-3-clg@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/ssi/aspeed_smc.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include/hw') diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 16c03fe..ccd71d9 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -103,9 +103,6 @@ struct AspeedSMCState { uint8_t r_timings; uint8_t conf_enable_w0; - /* for DMA support */ - uint64_t sdram_base; - AddressSpace flash_as; MemoryRegion *dram_mr; AddressSpace dram_as; -- cgit v1.1 From e9c568dbc22551f069dbc30ca3b61e168f494d47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 1 May 2021 10:03:51 +0200 Subject: hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The flash mmio region is exposed as an AddressSpace. AddressSpaces must not be sysbus-mapped, therefore map the region using an alias. Signed-off-by: Philippe Mathieu-Daudé [ clg : Fix DMA_FLASH_ADDR() ] Signed-off-by: Cédric Le Goater Message-Id: <20210312182851.1922972-3-f4bug@amsat.org> Signed-off-by: Cédric Le Goater Message-Id: <20210407171637.777743-6-clg@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/ssi/aspeed_smc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw') diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index ccd71d9..6ea2871 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -84,6 +84,7 @@ struct AspeedSMCState { MemoryRegion mmio; MemoryRegion mmio_flash; + MemoryRegion mmio_flash_alias; qemu_irq irq; int irqline; -- cgit v1.1 From c5475b3f9aa28c1c1422c7de0bab40c5dff77341 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Sat, 1 May 2021 10:03:51 +0200 Subject: hw: Model ASPEED's Hash and Crypto Engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1, SHA2, RSA and other cryptographic algorithms. This initial model implements a subset of the device's functionality; currently only MD5/SHA hashing, and on the ast2600's scatter gather engine. Co-developed-by: Klaus Heinrich Kiwi Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery [ clg: - fixes for 32-bit and OSX builds ] Signed-off-by: Cédric Le Goater Message-Id: <20210409000253.1475587-2-joel@jms.id.au> Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_hace.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 include/hw/misc/aspeed_hace.h (limited to 'include/hw') diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h new file mode 100644 index 0000000..94d5ada --- /dev/null +++ b/include/hw/misc/aspeed_hace.h @@ -0,0 +1,43 @@ +/* + * ASPEED Hash and Crypto Engine + * + * Copyright (C) 2021 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_HACE_H +#define ASPEED_HACE_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_HACE "aspeed.hace" +#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" +#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500" +#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600" +OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) + +#define ASPEED_HACE_NR_REGS (0x64 >> 2) + +struct AspeedHACEState { + SysBusDevice parent; + + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[ASPEED_HACE_NR_REGS]; + + MemoryRegion *dram_mr; + AddressSpace dram_as; +}; + + +struct AspeedHACEClass { + SysBusDeviceClass parent_class; + + uint32_t src_mask; + uint32_t dest_mask; + uint32_t hash_mask; +}; + +#endif /* _ASPEED_HACE_H_ */ -- cgit v1.1 From a3888d757acdd92c4c49fb9cad5f5733d8280a86 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Sat, 1 May 2021 10:03:51 +0200 Subject: aspeed: Integrate HACE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the hash and crypto engine model to the Aspeed socs. Reviewed-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Klaus Heinrich Kiwi Signed-off-by: Joel Stanley Message-Id: <20210409000253.1475587-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/hw') diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 9359d6d..d9161d2 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -21,6 +21,7 @@ #include "hw/rtc/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" +#include "hw/misc/aspeed_hace.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" @@ -50,6 +51,7 @@ struct AspeedSoCState { AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; AspeedSCUState scu; + AspeedHACEState hace; AspeedXDMAState xdma; AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; @@ -133,6 +135,7 @@ enum { ASPEED_DEV_XDMA, ASPEED_DEV_EMMC, ASPEED_DEV_KCS, + ASPEED_DEV_HACE, }; #endif /* ASPEED_SOC_H */ -- cgit v1.1 From 8efbee28f4729f16cae5cbf93a029bfa55198fc2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sat, 1 May 2021 10:03:52 +0200 Subject: hw/misc/aspeed_xdma: Add AST2600 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we introduced support for the AST2600 SoC, the XDMA controller was forgotten. It went unnoticed because it's not used under emulation. But the register layout being different, the reset procedure is bogus and this breaks kexec. Add a AspeedXDMAClass to take into account the register differences. Cc: Eddie James Signed-off-by: Cédric Le Goater Reviewed-by: Eddie James Message-Id: <20210407171637.777743-14-clg@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_xdma.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'include/hw') diff --git a/include/hw/misc/aspeed_xdma.h b/include/hw/misc/aspeed_xdma.h index a2dea96..b1478fd 100644 --- a/include/hw/misc/aspeed_xdma.h +++ b/include/hw/misc/aspeed_xdma.h @@ -13,7 +13,10 @@ #include "qom/object.h" #define TYPE_ASPEED_XDMA "aspeed.xdma" -OBJECT_DECLARE_SIMPLE_TYPE(AspeedXDMAState, ASPEED_XDMA) +#define TYPE_ASPEED_2400_XDMA TYPE_ASPEED_XDMA "-ast2400" +#define TYPE_ASPEED_2500_XDMA TYPE_ASPEED_XDMA "-ast2500" +#define TYPE_ASPEED_2600_XDMA TYPE_ASPEED_XDMA "-ast2600" +OBJECT_DECLARE_TYPE(AspeedXDMAState, AspeedXDMAClass, ASPEED_XDMA) #define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t)) #define ASPEED_XDMA_REG_SIZE 0x7C @@ -28,4 +31,16 @@ struct AspeedXDMAState { uint32_t regs[ASPEED_XDMA_NUM_REGS]; }; +struct AspeedXDMAClass { + SysBusDeviceClass parent_class; + + uint8_t cmdq_endp; + uint8_t cmdq_wrp; + uint8_t cmdq_rdp; + uint8_t intr_ctrl; + uint32_t intr_ctrl_mask; + uint8_t intr_status; + uint32_t intr_complete; +}; + #endif /* ASPEED_XDMA_H */ -- cgit v1.1 From 1c5ee69da5e65cc04055b304a784d82fd04de764 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sat, 1 May 2021 10:03:52 +0200 Subject: aspeed/smc: Add a 'features' attribute to the object class MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It will simplify extensions of the SMC model. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-Id: <20210407171637.777743-15-clg@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/ssi/aspeed_smc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/hw') diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 6ea2871..07879fd 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -47,7 +47,7 @@ typedef struct AspeedSMCController { const AspeedSegments *segments; hwaddr flash_window_base; uint32_t flash_window_size; - bool has_dma; + uint32_t features; hwaddr dma_flash_mask; hwaddr dma_dram_mask; uint32_t nregs; -- cgit v1.1 From 1769a70e54181bb3e54783f16350892e847a3a89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sat, 1 May 2021 10:03:52 +0200 Subject: aspeed/smc: Add extra controls to request DMA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The AST2600 SPI controllers have a set of bits to request/grant DMA access. Add a new SMC feature for these controllers and use it to check access to the DMA registers. Cc: Chin-Ting Kuo Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley Message-Id: <20210407171637.777743-16-clg@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/ssi/aspeed_smc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw') diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 07879fd..cdaf165 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -55,6 +55,7 @@ typedef struct AspeedSMCController { const AspeedSegments *seg); void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg, AspeedSegments *seg); + void (*dma_ctrl)(struct AspeedSMCState *s, uint32_t value); } AspeedSMCController; typedef struct AspeedSMCFlash { -- cgit v1.1