From 4b19de14b145ac1df3082f625e3b8f9dcb0e1918 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 15 Oct 2019 14:05:42 +0200 Subject: hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Acked-by: Paul Durrant Reviewed-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daudé --- include/hw/southbridge/piix.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/hw') diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index e49d4a6..094508b 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, qemu_irq sci_irq, qemu_irq smi_irq, int smm_enabled, DeviceState **piix4_pm); +/* PIRQRC[A:D]: PIRQx Route Control Registers */ +#define PIIX_PIRQCA 0x60 +#define PIIX_PIRQCB 0x61 +#define PIIX_PIRQCC 0x62 +#define PIIX_PIRQCD 0x63 + /* * Reset Control Register: PCI-accessible ISA-Compatible Register at address * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). -- cgit v1.1