From 14c179541bbf083f4b215ddb389828ad8b9d0b28 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 1 Sep 2020 14:21:51 +0200 Subject: aspeed/sdmc: Perform memory training MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows qemu to run the "normal" power on reset boot path through u-boot, where the DDR is trained. An enhancement would be to have the SCU bit stick across qemu reboots, but be unset on initial boot. Proper modelling would be to discard all writes to the phy setting regs at offset 0x100 - 0x400 and to model the phy status regs at offset 0x400. The status regs model would only need to account for offets 0x00, 0x50, 0x68 and 0x7c. Signed-off-by: Joel Stanley [ clg: checkpatch fixes ] Message-Id: <20200819100956.2216690-17-clg@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_sdmc.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include/hw') diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index cea1e67..c622695 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -17,7 +17,18 @@ #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" #define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" -#define ASPEED_SDMC_NR_REGS (0x174 >> 2) +/* + * SDMC has 174 documented registers. In addition the u-boot device tree + * describes the following regions: + * - PHY status regs at offset 0x400, length 0x200 + * - PHY setting regs at offset 0x100, length 0x300 + * + * There are two sets of MRS (Mode Registers) configuration in ast2600 memory + * system: one is in the SDRAM MC (memory controller) which is used in run + * time, and the other is in the DDR-PHY IP which is used during DDR-PHY + * training. + */ +#define ASPEED_SDMC_NR_REGS (0x500 >> 2) typedef struct AspeedSDMCState { /*< private >*/ -- cgit v1.1 From d98c48a19fe8f9e9627802b5b7de16189632d5c9 Mon Sep 17 00:00:00 2001 From: Igor Kononenko Date: Tue, 1 Sep 2020 14:21:51 +0200 Subject: arm: aspeed: add strap define `25HZ` of AST2500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provide a definition for the "25Hz reference clock input mode" strap Signed-off-by: Igor Kononenko Reviewed-by: Cédric Le Goater Message-Id: <20200811203502.20382-1-i.kononenko@yadro.com> Message-Id: <20200819100956.2216690-21-clg@kaod.org> Signed-off-by: Cédric Le Goater --- include/hw/misc/aspeed_scu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw') diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index a6739bb..9cd530a 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -286,6 +286,7 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) +#define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23) #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) -- cgit v1.1