From da71b7e3ed454bd9200367e09bf75160f8f097a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Mar 2022 06:51:38 +0100 Subject: ppc/pnv: Add a XIVE2 controller to the POWER10 chip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The XIVE2 interrupt controller of the POWER10 processor follows the same logic than on POWER9 but the HW interface has been largely reviewed. It has a new register interface, different BARs, extra VSDs, new layout for the XIVE2 structures, and a set of new features which are described below. This is a model of the POWER10 XIVE2 interrupt controller for the PowerNV machine. It focuses primarily on the needs of the skiboot firmware but some initial hypervisor support is implemented for KVM use (escalation). Support for new features will be implemented in time and will require new support from the OS. * XIVE2 BARS The interrupt controller BARs have a different layout outlined below. Each sub-engine has now own its range and the indirect TIMA access was replaced with a set of pages, one per CPU, under the IC BAR: - IC BAR (Interrupt Controller) . 4 pages, one per sub-engine . 128 indirect TIMA pages - TM BAR (Thread Interrupt Management Area) . 4 pages - ESB BAR (ESB pages for IPIs) . up to 1TB - END BAR (ESB pages for ENDs) . up to 2TB - NVC BAR (Notification Virtual Crowd) . up to 128 - NVPG BAR (Notification Virtual Process and Group) . up to 1TB - Direct mapped Thread Context Area (reads & writes) OPAL does not use the grouping and crowd capability. * Virtual Structure Tables XIVE2 adds new tables types and also changes the field layout of the END and NVP Virtualization Structure Descriptors. - EAS - END new layout - NVT was splitted in : . NVP (Processor), 32B . NVG (Group), 32B . NVC (Crowd == P9 block group) 32B - IC for remote configuration - SYNC for cache injection - ERQ for event input queue The setup is slighly different on XIVE2 because the indexing has changed for some of the tables, block ID or the chip topology ID can be used. * XIVE2 features SCOM and MMIO registers have a new layout and XIVE2 adds a new global capability and configuration registers. The lowlevel hardware offers a set of new features among which : - a configurable number of priorities : 1 - 8 - StoreEOI with load-after-store ordering is activated by default - Gen2 TIMA layout - A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility - increase to 24bit for VP number Other features will have some impact on the Hypervisor and guest OS when activated, but this is not required for initial support of the controller. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include/hw/ppc/pnv.h') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 0e9e165..6b3457b 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -125,10 +125,14 @@ struct Pnv10Chip { PnvChip parent_obj; /*< public >*/ + PnvXive2 xive; Pnv9Psi psi; PnvLpcController lpc; }; +#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) + struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; @@ -329,10 +333,28 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV10_LPCM_SIZE 0x0000000100000000ull #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) +#define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull +#define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull) + #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) #define PNV10_PSIHB_SIZE 0x0000000000100000ull #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) +#define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull +#define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull) + +#define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull +#define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull) + +#define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull +#define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull) + +#define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull +#define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull) + +#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull +#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull) + #endif /* PPC_PNV_H */ -- cgit v1.1 From 8bf682a349258c3d4a4a4d4fa99ecf7045cf4608 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Mar 2022 06:51:39 +0100 Subject: ppc/pnv: Add a OCC model for POWER10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Our OCC model is very mininal and POWER10 can simply reuse the OCC model we introduced for POWER9. Reviewed-by: David Gibson Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/ppc/pnv.h') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 6b3457b..21e69b0 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -128,6 +128,7 @@ struct Pnv10Chip { PnvXive2 xive; Pnv9Psi psi; PnvLpcController lpc; + PnvOCC occ; }; #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) -- cgit v1.1 From ae4c68e366d68058cd50318d1716fb59c63f4907 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Mar 2022 06:51:39 +0100 Subject: ppc/pnv: Add POWER10 quads MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit and use a pnv_chip_power10_quad_realize() helper to avoid code duplication with P9. This still needs some refinements on the XSCOM registers handling in PnvQuad. Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/hw/ppc/pnv.h') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 21e69b0..6449fba 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -129,6 +129,9 @@ struct Pnv10Chip { Pnv9Psi psi; PnvLpcController lpc; PnvOCC occ; + + uint32_t nr_quads; + PnvQuad *quads; }; #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) -- cgit v1.1 From 623575e16cd55082ca36b57114a774f146b2c95b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Mar 2022 06:51:39 +0100 Subject: ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PHB4 and PHB5 are very similar. Use the PHB4 models with some minor adjustements in a subclass for P10. Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/hw/ppc/pnv.h') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 6449fba..e514185 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -132,6 +132,9 @@ struct Pnv10Chip { uint32_t nr_quads; PnvQuad *quads; + +#define PNV10_CHIP_MAX_PEC 2 + PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; }; #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) -- cgit v1.1 From 924996766b428dfe266df6778a7114e0c9f609ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Mar 2022 06:51:39 +0100 Subject: ppc/pnv: Add a HOMER model to POWER10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: David Gibson Signed-off-by: Cédric Le Goater --- include/hw/ppc/pnv.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/hw/ppc/pnv.h') diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index e514185..1e34ddd 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -129,6 +129,7 @@ struct Pnv10Chip { Pnv9Psi psi; PnvLpcController lpc; PnvOCC occ; + PnvHomer homer; uint32_t nr_quads; PnvQuad *quads; @@ -364,4 +365,13 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull) +#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull +#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull +#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \ + PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) + +#define PNV10_HOMER_SIZE 0x0000000000400000ull +#define PNV10_HOMER_BASE(chip) \ + (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE) + #endif /* PPC_PNV_H */ -- cgit v1.1