From 51fd06e0eee8257fdcc147200796e362cf2298ea Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Sep 2015 17:38:42 +0100 Subject: hw/intc/arm_gic: Fix handling of GICC_APR, GICC_NSAPR registers A GICv2 has both GICC_APR and GICC_NSAPR registers, with the latter holding the active priority bits for Group 1 interrupts (usually Nonsecure interrupts), and the Nonsecure view of the GICC_APR is the second half of the GICC_NSAPR registers. Turn our half-hearted implementation of APR into a proper implementation of both APR and NSAPR: * Add the underlying state for NSAPR * Make sure APR aren't visible for pre-GICv2 * Implement reading of NSAPR * Make non-secure reads of APR behave correctly * Implement writing to APR and NSAPR Signed-off-by: Peter Maydell Message-id: 1438089748-5528-4-git-send-email-peter.maydell@linaro.org --- include/hw/intc/arm_gic_common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/intc') diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index edca3e0..c4ec2c3 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -106,6 +106,7 @@ typedef struct GICState { * the GIC. */ uint32_t apr[GIC_NR_APRS][GIC_NCPU]; + uint32_t nsapr[GIC_NR_APRS][GIC_NCPU]; uint32_t num_cpu; -- cgit v1.1