From 5454006a7cc6caf10c1816e6828b75a40fbcc16e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 20 Jan 2017 11:15:09 +0000 Subject: hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Wire the new VIRQ, VFIQ and maintenance interrupt lines from the GIC to each CPU. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Message-id: 1483977924-14522-5-git-send-email-peter.maydell@linaro.org --- include/hw/arm/virt.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/hw/arm') diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index eb1c63d..b8a19ec 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -39,6 +39,8 @@ #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 +#define ARCH_GICV3_MAINT_IRQ 9 + #define ARCH_TIMER_VIRT_IRQ 11 #define ARCH_TIMER_S_EL1_IRQ 13 #define ARCH_TIMER_NS_EL1_IRQ 14 -- cgit v1.1