From ccc3ee38713381a823a6b9229b36a0a1b36d919d Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:51 +0100 Subject: hw/arm/smmuv3: Add CMDs related to stage-2 CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the same as CMD_TLBI_NH_VAA. CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID. For stage-1 only commands, add a check to throw CERROR_ILL if used when stage-1 is not supported. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-9-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/arm/smmu-common.h') diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 3cbb499..fd8d772 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -193,6 +193,7 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); +void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); -- cgit v1.1