From f0a902f76452211cadbdf1d25ef9b94732b096e8 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Thu, 14 May 2015 19:22:58 -0700 Subject: arm: Introduce Xilinx ZynqMP SoC With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Crosthwaite Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-zynqmp.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 hw/arm/xlnx-zynqmp.c (limited to 'hw') diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 2577f68..d7cd5f4 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -10,3 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o obj-y += omap1.o omap2.o strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o +obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c new file mode 100644 index 0000000..ec0ebaa --- /dev/null +++ b/hw/arm/xlnx-zynqmp.c @@ -0,0 +1,76 @@ +/* + * Xilinx Zynq MPSoC emulation + * + * Copyright (C) 2015 Xilinx Inc + * Written by Peter Crosthwaite + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "hw/arm/xlnx-zynqmp.h" + +static void xlnx_zynqmp_init(Object *obj) +{ + XlnxZynqMPState *s = XLNX_ZYNQMP(obj); + int i; + + for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { + object_initialize(&s->cpu[i], sizeof(s->cpu[i]), + "cortex-a53-" TYPE_ARM_CPU); + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), + &error_abort); + } +} + +static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPState *s = XLNX_ZYNQMP(dev); + uint8_t i; + Error *err = NULL; + + for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { + object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC, + "psci-conduit", &error_abort); + if (i > 0) { + /* Secondary CPUs start in PSCI powered-down state */ + object_property_set_bool(OBJECT(&s->cpu[i]), true, + "start-powered-off", &error_abort); + } + + object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); + if (err) { + error_propagate((errp), (err)); + return; + } + } +} + +static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = xlnx_zynqmp_realize; +} + +static const TypeInfo xlnx_zynqmp_type_info = { + .name = TYPE_XLNX_ZYNQMP, + .parent = TYPE_DEVICE, + .instance_size = sizeof(XlnxZynqMPState), + .instance_init = xlnx_zynqmp_init, + .class_init = xlnx_zynqmp_class_init, +}; + +static void xlnx_zynqmp_register_types(void) +{ + type_register_static(&xlnx_zynqmp_type_info); +} + +type_init(xlnx_zynqmp_register_types) -- cgit v1.1