From e99fd8af63a1692a1159cba8fa4943f2589adf97 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 21 Dec 2012 16:15:39 +0000 Subject: openpic: lower interrupt when reading the MSI register This will stop things from breaking once it's properly treated as a level-triggered interrupt. Note that it's the MPIC's MSI cascade interrupts that are level-triggered; the individual MSIs are edge-triggered. Signed-off-by: Scott Wood Signed-off-by: Alexander Graf --- hw/openpic.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/openpic.c b/hw/openpic.c index 9243e70..f4df66d 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -810,6 +810,7 @@ static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) r = opp->msi[srs].msir; /* Clear on read */ opp->msi[srs].msir = 0; + openpic_set_irq(opp, opp->irq_msi + srs, 0); break; case 0x120: /* MSISR */ for (i = 0; i < MAX_MSI; i++) { -- cgit v1.1