From b7174d9ad3ec3966270eeefa965ffe8f336b86dd Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 2 Feb 2024 21:05:56 +0100 Subject: hw/pci-host/astro: Avoid aborting on access failure Instead of stopping the emulation, report a MEMTX_DECODE_ERROR if the OS tries to access non-existent registers. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- hw/pci-host/astro.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 37d2711..96d655f 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -122,10 +122,6 @@ static MemTxResult elroy_chip_read_with_attrs(void *opaque, hwaddr addr, case 0x0800: /* IOSAPIC_REG_SELECT */ val = s->iosapic_reg_select; break; - case 0x0808: - val = UINT64_MAX; /* XXX: tbc. */ - g_assert_not_reached(); - break; case 0x0810: /* IOSAPIC_REG_WINDOW */ switch (s->iosapic_reg_select) { case 0x01: /* IOSAPIC_REG_VERSION */ @@ -135,15 +131,15 @@ static MemTxResult elroy_chip_read_with_attrs(void *opaque, hwaddr addr, if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) { val = s->iosapic_reg[s->iosapic_reg_select]; } else { - trace_iosapic_reg_read(s->iosapic_reg_select, size, val); - g_assert_not_reached(); + val = 0; + ret = MEMTX_DECODE_ERROR; } } trace_iosapic_reg_read(s->iosapic_reg_select, size, val); break; default: - trace_elroy_read(addr, size, val); - g_assert_not_reached(); + val = 0; + ret = MEMTX_DECODE_ERROR; } trace_elroy_read(addr, size, val); @@ -191,7 +187,7 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr, if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) { s->iosapic_reg[s->iosapic_reg_select] = val; } else { - g_assert_not_reached(); + return MEMTX_DECODE_ERROR; } break; case 0x0840: /* IOSAPIC_REG_EOI */ @@ -204,7 +200,7 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr, } break; default: - g_assert_not_reached(); + return MEMTX_DECODE_ERROR; } return MEMTX_OK; } @@ -594,8 +590,8 @@ static MemTxResult astro_chip_read_with_attrs(void *opaque, hwaddr addr, #undef EMPTY_PORT default: - trace_astro_chip_read(addr, size, val); - g_assert_not_reached(); + val = 0; + ret = MEMTX_DECODE_ERROR; } /* for 32-bit accesses mask return value */ @@ -610,6 +606,7 @@ static MemTxResult astro_chip_write_with_attrs(void *opaque, hwaddr addr, uint64_t val, unsigned size, MemTxAttrs attrs) { + MemTxResult ret = MEMTX_OK; AstroState *s = opaque; trace_astro_chip_write(addr, size, val); @@ -686,11 +683,9 @@ static MemTxResult astro_chip_write_with_attrs(void *opaque, hwaddr addr, #undef EMPTY_PORT default: - /* Controlled by astro_chip_mem_valid above. */ - trace_astro_chip_write(addr, size, val); - g_assert_not_reached(); + ret = MEMTX_DECODE_ERROR; } - return MEMTX_OK; + return ret; } static const MemoryRegionOps astro_chip_ops = { -- cgit v1.1 From f410b688af8fa6b317c58dd1a11f2b3225d4a0ea Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 2 Feb 2024 21:28:50 +0100 Subject: hw/pci-host/astro: Implement Hard Fail and Soft Fail mode The Astro/Elroy chip can work in either Hard-Fail or Soft-Fail mode. Hard fail means the system bus will send an HPMC (=crash) to the processor, soft fail means the system bus will ignore timeouts of MMIO-reads or MMIO-writes and return -1ULL. The HF mode is controlled by a bit in the status register and is usually programmed by the OS. Return the corresponing values based on the current value of that bit. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson --- hw/pci-host/astro.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 96d655f..e3e589c 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -131,15 +131,21 @@ static MemTxResult elroy_chip_read_with_attrs(void *opaque, hwaddr addr, if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) { val = s->iosapic_reg[s->iosapic_reg_select]; } else { - val = 0; - ret = MEMTX_DECODE_ERROR; + goto check_hf; } } trace_iosapic_reg_read(s->iosapic_reg_select, size, val); break; default: - val = 0; - ret = MEMTX_DECODE_ERROR; + check_hf: + if (s->status_control & HF_ENABLE) { + val = 0; + ret = MEMTX_DECODE_ERROR; + } else { + /* return -1ULL if HardFail is disabled */ + val = ~0; + ret = MEMTX_OK; + } } trace_elroy_read(addr, size, val); @@ -187,7 +193,7 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr, if (s->iosapic_reg_select < ARRAY_SIZE(s->iosapic_reg)) { s->iosapic_reg[s->iosapic_reg_select] = val; } else { - return MEMTX_DECODE_ERROR; + goto check_hf; } break; case 0x0840: /* IOSAPIC_REG_EOI */ @@ -200,7 +206,10 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr, } break; default: - return MEMTX_DECODE_ERROR; + check_hf: + if (s->status_control & HF_ENABLE) { + return MEMTX_DECODE_ERROR; + } } return MEMTX_OK; } -- cgit v1.1 From f2ffd6fb4059d22e18b23c2112419320345aeacf Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 2 Feb 2024 22:53:08 +0100 Subject: lasi: allow access to LAN MAC address registers Firmware and qemu reads and writes the MAC address for the LASI LAN via registers in LASI. Allow those accesses and return zero even if LASI LAN isn't enabled to avoid HPMCs (=crashes). Signed-off-by: Helge Deller --- hw/misc/lasi.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw') diff --git a/hw/misc/lasi.c b/hw/misc/lasi.c index 003f5b5..9cfa5bb 100644 --- a/hw/misc/lasi.c +++ b/hw/misc/lasi.c @@ -38,6 +38,7 @@ static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, case LASI_LPT: case LASI_UART: case LASI_LAN: + case LASI_LAN + 12: /* LASI LAN MAC */ case LASI_RTC: case LASI_PCR ... LASI_AMR: @@ -78,6 +79,7 @@ static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, case LASI_LPT: case LASI_UART: case LASI_LAN: + case LASI_LAN + 12: val = 0; break; case LASI_RTC: -- cgit v1.1 From 32d26ea407cadf6efbb46c972caf8594a45c4c81 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Sat, 3 Feb 2024 01:04:45 +0100 Subject: lasi: Add reset I/O ports for LASI audio and FDC Linux writes zeroes at bootup into the default ports for LASI audio and LASI floppy controller to reset those devices. Allow writing to those registers to avoid HPMCs. Signed-off-by: Helge Deller --- hw/misc/lasi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'hw') diff --git a/hw/misc/lasi.c b/hw/misc/lasi.c index 9cfa5bb..970fc98 100644 --- a/hw/misc/lasi.c +++ b/hw/misc/lasi.c @@ -36,10 +36,13 @@ static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, case LASI_IAR: case LASI_LPT: + case LASI_AUDIO: + case LASI_AUDIO + 4: case LASI_UART: case LASI_LAN: case LASI_LAN + 12: /* LASI LAN MAC */ case LASI_RTC: + case LASI_FDC: case LASI_PCR ... LASI_AMR: ret = true; @@ -80,6 +83,7 @@ static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, case LASI_UART: case LASI_LAN: case LASI_LAN + 12: + case LASI_FDC: val = 0; break; case LASI_RTC: @@ -145,12 +149,19 @@ static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr, case LASI_LPT: /* XXX: reset parallel port */ break; + case LASI_AUDIO: + case LASI_AUDIO + 4: + /* XXX: reset audio port */ + break; case LASI_UART: /* XXX: reset serial port */ break; case LASI_LAN: /* XXX: reset LAN card */ break; + case LASI_FDC: + /* XXX: reset Floppy controller */ + break; case LASI_RTC: s->rtc_ref = val - time(NULL); break; -- cgit v1.1 From 9b60a3ed5569a70bbdd29e3c9ec4c5d4685c6e2c Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Mon, 5 Feb 2024 20:47:17 +0100 Subject: hw/net/tulip: add chip status register values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Netbsd isn't able to detect a link on the emulated tulip card. That's because netbsd reads the Chip Status Register of the Phy (address 0x14). The default phy data in the qemu tulip driver is all zero, which means no link is established and autonegotation isn't complete. Therefore set the register to 0x3b40, which means: Link is up, Autonegotation complete, Full Duplex, 100MBit/s Link speed. Also clear the mask because this register is read only. Signed-off-by: Sven Schnelle Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller Tested-by: Helge Deller Signed-off-by: Helge Deller --- hw/net/tulip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/net/tulip.c b/hw/net/tulip.c index 6d4fb06..1f2ef20 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -421,7 +421,7 @@ static uint16_t tulip_mdi_default[] = { /* MDI Registers 8 - 15 */ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* MDI Registers 16 - 31 */ - 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0003, 0x0000, 0x0001, 0x0000, 0x3b40, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; @@ -429,7 +429,7 @@ static uint16_t tulip_mdi_default[] = { static const uint16_t tulip_mdi_mask[] = { 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0x0fff, 0x0000, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; -- cgit v1.1 From a9314795f068515ff5925d0f68adf0a3215f6d2d Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 2 Feb 2024 16:22:38 +0100 Subject: hw/hppa/machine: Load 64-bit firmware on 64-bit machines Load the 64-bit SeaBIOS-hppa firmware by default when running on a 64-bit machine. This will enable us to later support more than 4GB of RAM and is required that the OS (or PALO bootloader) will start or install a 64-bit kernel instead of a 32-bit kernel. Note that SeaBIOS-hppa v16 provides the "-fw_cfg opt/OS64,string=3" option with which the user can control what the firmware shall report back to the OS: Support of 32-bit OS, support of a 64-bit OS, or support for both (default). Wrap firmware loading inside !qtest_enabled() to avoid this warning with qtest: "qemu-system-hppa: no firmware provided". Signed-off-by: Helge Deller Acked-by: Richard Henderson --- hw/hppa/machine.c | 52 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 22 deletions(-) (limited to 'hw') diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index eb78c46..5fcaf58 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -13,6 +13,7 @@ #include "qemu/error-report.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" +#include "sysemu/qtest.h" #include "sysemu/runstate.h" #include "hw/rtc/mc146818rtc.h" #include "hw/timer/i8254.h" @@ -333,6 +334,7 @@ static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus, const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; + const char *firmware = machine->firmware; MachineClass *mc = MACHINE_GET_CLASS(machine); DeviceState *dev; PCIDevice *pci_dev; @@ -408,31 +410,37 @@ static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus, /* Load firmware. Given that this is not "real" firmware, but one explicitly written for the emulation, we might as - well load it directly from an ELF image. */ - firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, - machine->firmware ?: "hppa-firmware.img"); - if (firmware_filename == NULL) { - error_report("no firmware provided"); - exit(1); - } + well load it directly from an ELF image. Load the 64-bit + firmware on 64-bit machines by default if not specified + on command line. */ + if (!qtest_enabled()) { + if (!firmware) { + firmware = lasi_dev ? "hppa-firmware.img" : "hppa-firmware64.img"; + } + firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware); + if (firmware_filename == NULL) { + error_report("no firmware provided"); + exit(1); + } - size = load_elf(firmware_filename, NULL, translate, NULL, - &firmware_entry, &firmware_low, &firmware_high, NULL, - true, EM_PARISC, 0, 0); + size = load_elf(firmware_filename, NULL, translate, NULL, + &firmware_entry, &firmware_low, &firmware_high, NULL, + true, EM_PARISC, 0, 0); - if (size < 0) { - error_report("could not load firmware '%s'", firmware_filename); - exit(1); - } - qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64 - "-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n", - firmware_low, firmware_high, firmware_entry); - if (firmware_low < translate(NULL, FIRMWARE_START) || - firmware_high >= translate(NULL, FIRMWARE_END)) { - error_report("Firmware overlaps with memory or IO space"); - exit(1); + if (size < 0) { + error_report("could not load firmware '%s'", firmware_filename); + exit(1); + } + qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64 + "-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n", + firmware_low, firmware_high, firmware_entry); + if (firmware_low < translate(NULL, FIRMWARE_START) || + firmware_high >= translate(NULL, FIRMWARE_END)) { + error_report("Firmware overlaps with memory or IO space"); + exit(1); + } + g_free(firmware_filename); } - g_free(firmware_filename); rom_region = g_new(MemoryRegion, 1); memory_region_init_ram(rom_region, NULL, "firmware", -- cgit v1.1