From bba5ed772a562fefdb218df8d821c3b537ce5759 Mon Sep 17 00:00:00 2001 From: Isaku Yamahata Date: Fri, 19 Nov 2010 13:28:45 +0200 Subject: pcie/port: fix bridge control register wmask pci generic layer initialized wmask for bridge control register according to pci spec. pcie deviates slightly from it, so initialize it properly. Signed-off-by: Isaku Yamahata Signed-off-by: Michael S. Tsirkin --- hw/pcie_port.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'hw') diff --git a/hw/pcie_port.c b/hw/pcie_port.c index 117de61..340dcdb 100644 --- a/hw/pcie_port.c +++ b/hw/pcie_port.c @@ -27,6 +27,14 @@ void pcie_port_init_reg(PCIDevice *d) pci_set_word(d->config + PCI_STATUS, 0); pci_set_word(d->config + PCI_SEC_STATUS, 0); + /* Unlike conventional pci bridge, some bits are hardwared to 0. */ + pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, + PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_ISA | + PCI_BRIDGE_CTL_VGA | + PCI_BRIDGE_CTL_SERR | + PCI_BRIDGE_CTL_BUS_RESET); + /* 7.5.3.5 Prefetchable Memory Base Limit * The Prefetchable Memory Base and Prefetchable Memory Limit registers * must indicate that 64-bit addresses are supported, as defined in -- cgit v1.1