From b6889c5ae3895cf5a4322adb32b2133e9b91d158 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 10 May 2021 20:08:39 +0100 Subject: hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524 The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model it that way in hw/arm/armsse.c (along with the associated MPCs). We incorrectly also added an entry to the RAMInfo array for the AN524 in hw/arm/mps2-tz.c, which was pointless because the CPU would never see it. Delete it. The bug had no guest-visible effect because devices in the SSE-200 take priority over those in the board model (armsse.c maps s->board_memory at priority -2). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210510190844.17799-2-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'hw') diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 70aa31a..77ff83a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -244,18 +244,12 @@ static const RAMInfo an524_raminfo[] = { { .mpc = 0, .mrindex = 0, }, { - .name = "sram", - .base = 0x20000000, - .size = 32 * 4 * KiB, - .mpc = -1, - .mrindex = 1, - }, { /* We don't model QSPI flash yet; for now expose it as simple ROM */ .name = "QSPI", .base = 0x28000000, .size = 8 * MiB, .mpc = 1, - .mrindex = 2, + .mrindex = 1, .flags = IS_ROM, }, { .name = "DDR", -- cgit v1.1