From af2a580f7e09359f882014e47a91e620a325537b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 11 Nov 2019 13:44:16 +0000 Subject: ptimer: Remove old ptimer_init_with_bh() API Now all the users of ptimers have converted to the transaction-based API, we can remove ptimer_init_with_bh() and all the code paths that are used only by bottom-half based ptimers, and tidy up the documentation comments to consider the transaction-based API the only possibility. The code changes result from: * s->bh no longer exists * s->callback is now always non-NULL Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20191025142411.17085-1-peter.maydell@linaro.org --- hw/core/ptimer.c | 91 ++++++++++---------------------------------------------- 1 file changed, 15 insertions(+), 76 deletions(-) (limited to 'hw') diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index 7239b82..b5a54e2 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -29,7 +29,6 @@ struct ptimer_state int64_t last_event; int64_t next_event; uint8_t policy_mask; - QEMUBH *bh; QEMUTimer *timer; ptimer_cb callback; void *callback_opaque; @@ -46,12 +45,7 @@ struct ptimer_state /* Use a bottom-half routine to avoid reentrancy issues. */ static void ptimer_trigger(ptimer_state *s) { - if (s->bh) { - replay_bh_schedule_event(s->bh); - } - if (s->callback) { - s->callback(s->callback_opaque); - } + s->callback(s->callback_opaque); } static void ptimer_reload(ptimer_state *s, int delta_adjust) @@ -296,15 +290,10 @@ uint64_t ptimer_get_count(ptimer_state *s) void ptimer_set_count(ptimer_state *s, uint64_t count) { - assert(s->in_transaction || !s->callback); + assert(s->in_transaction); s->delta = count; if (s->enabled) { - if (!s->callback) { - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); - } else { - s->need_reload = true; - } + s->need_reload = true; } } @@ -312,7 +301,7 @@ void ptimer_run(ptimer_state *s, int oneshot) { bool was_disabled = !s->enabled; - assert(s->in_transaction || !s->callback); + assert(s->in_transaction); if (was_disabled && s->period == 0) { if (!qtest_enabled()) { @@ -322,12 +311,7 @@ void ptimer_run(ptimer_state *s, int oneshot) } s->enabled = oneshot ? 2 : 1; if (was_disabled) { - if (!s->callback) { - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); - } else { - s->need_reload = true; - } + s->need_reload = true; } } @@ -335,7 +319,7 @@ void ptimer_run(ptimer_state *s, int oneshot) is immediately restarted. */ void ptimer_stop(ptimer_state *s) { - assert(s->in_transaction || !s->callback); + assert(s->in_transaction); if (!s->enabled) return; @@ -343,42 +327,30 @@ void ptimer_stop(ptimer_state *s) s->delta = ptimer_get_count(s); timer_del(s->timer); s->enabled = 0; - if (s->callback) { - s->need_reload = false; - } + s->need_reload = false; } /* Set counter increment interval in nanoseconds. */ void ptimer_set_period(ptimer_state *s, int64_t period) { - assert(s->in_transaction || !s->callback); + assert(s->in_transaction); s->delta = ptimer_get_count(s); s->period = period; s->period_frac = 0; if (s->enabled) { - if (!s->callback) { - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); - } else { - s->need_reload = true; - } + s->need_reload = true; } } /* Set counter frequency in Hz. */ void ptimer_set_freq(ptimer_state *s, uint32_t freq) { - assert(s->in_transaction || !s->callback); + assert(s->in_transaction); s->delta = ptimer_get_count(s); s->period = 1000000000ll / freq; s->period_frac = (1000000000ll << 32) / freq; if (s->enabled) { - if (!s->callback) { - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); - } else { - s->need_reload = true; - } + s->need_reload = true; } } @@ -386,17 +358,12 @@ void ptimer_set_freq(ptimer_state *s, uint32_t freq) count = limit. */ void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) { - assert(s->in_transaction || !s->callback); + assert(s->in_transaction); s->limit = limit; if (reload) s->delta = limit; if (s->enabled && reload) { - if (!s->callback) { - s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - ptimer_reload(s, 0); - } else { - s->need_reload = true; - } + s->need_reload = true; } } @@ -407,7 +374,7 @@ uint64_t ptimer_get_limit(ptimer_state *s) void ptimer_transaction_begin(ptimer_state *s) { - assert(!s->in_transaction || !s->callback); + assert(!s->in_transaction); s->in_transaction = true; s->need_reload = false; } @@ -448,37 +415,12 @@ const VMStateDescription vmstate_ptimer = { } }; -ptimer_state *ptimer_init_with_bh(QEMUBH *bh, uint8_t policy_mask) -{ - ptimer_state *s; - - s = (ptimer_state *)g_malloc0(sizeof(ptimer_state)); - s->bh = bh; - s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); - s->policy_mask = policy_mask; - - /* - * These two policies are incompatible -- trigger-on-decrement implies - * a timer trigger when the count becomes 0, but no-immediate-trigger - * implies a trigger when the count stops being 0. - */ - assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && - (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); - return s; -} - ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, uint8_t policy_mask) { ptimer_state *s; - /* - * The callback function is mandatory; so we use it to distinguish - * old-style QEMUBH ptimers from new transaction API ptimers. - * (ptimer_init_with_bh() allows a NULL bh pointer and at least - * one device (digic-timer) passes NULL, so it's not the case - * that either s->bh != NULL or s->callback != NULL.) - */ + /* The callback function is mandatory. */ assert(callback); s = g_new0(ptimer_state, 1); @@ -499,9 +441,6 @@ ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, void ptimer_free(ptimer_state *s) { - if (s->bh) { - qemu_bh_delete(s->bh); - } timer_free(s->timer); g_free(s); } -- cgit v1.1 From 45c078f163fd47c35e7505d98928fae63baada7d Mon Sep 17 00:00:00 2001 From: Clement Deschamps Date: Mon, 11 Nov 2019 13:44:16 +0000 Subject: hw/arm/boot: Set NSACR.{CP11, CP10} in dummy SMC setup routine The boot.c code usually puts the CPU into NS mode directly when it is booting a kernel. Since fc1120a7f5f2d4b6 this has included a requirement to set NSACR to give NS state access to the FPU; we fixed that for the usual code path in ece628fcf6. However, it is also possible for a board model to request an alternative mode of booting, where its 'board_setup' code hook runs in Secure state and is responsible for doing the S->NS transition after it has done whatever work it must do in Secure state. In this situation the board_setup code now also needs to update NSACR. This affects all boards which set info->secure_board_setup, which is currently the 'raspi' and 'highbank' families. They both use the common arm_write_secure_board_setup_dummy_smc(). Set the NSACR CP11 and CP10 bits in the code written by that function, to allow FPU access in Non-Secure state when using dummy SMC setup routine. Otherwise an AArch32 kernel booted on the highbank or raspi boards will UNDEF as soon as it tries to use the FPU. Update the comment describing secure_board_setup to note the new requirements on users of it. This fixes a kernel panic when booting raspbian on raspi2. Successfully tested with: 2017-01-11-raspbian-jessie-lite.img 2018-11-13-raspbian-stretch-lite.img 2019-07-10-raspbian-buster-lite.img Fixes: fc1120a7f5 Signed-off-by: Clement Deschamps Tested-by: Laurent Bonnans Message-id: 20191104151137.81931-1-clement.deschamps@greensocs.com Reviewed-by: Peter Maydell [PMM: updated comment to boot.h to note new requirement on users of secure_board_setup; edited/rewrote commit message] Signed-off-by: Peter Maydell --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'hw') diff --git a/hw/arm/boot.c b/hw/arm/boot.c index ef67249..8fb4a63 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -240,6 +240,9 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, }; uint32_t board_setup_blob[] = { /* board setup addr */ + 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ + 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ + 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ -- cgit v1.1