From 2eaaac1f01014bc7a3597847646a814539494fca Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 7 Nov 2014 16:50:44 +0100 Subject: PPC: e500: Move CCSR definition to params We want to have different MMIO region offsets for the mpc8544ds machine and our e500 PV machine, so move the definitions of those into the machine specific params struct. Signed-off-by: Alexander Graf --- hw/ppc/e500.c | 30 ++++++++++++++---------------- hw/ppc/e500.h | 3 +++ hw/ppc/e500plat.c | 3 +++ hw/ppc/mpc8544ds.c | 3 +++ 4 files changed, 23 insertions(+), 16 deletions(-) (limited to 'hw') diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 2832fc0..1aaa515 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -51,19 +51,14 @@ #define RAM_SIZES_ALIGN (64UL << 20) /* TODO: parameterize */ -#define MPC8544_CCSRBAR_BASE 0xE0000000ULL #define MPC8544_CCSRBAR_SIZE 0x00100000ULL #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL #define MPC8544_MSI_REGS_OFFSET 0x41600ULL #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL #define MPC8544_PCI_REGS_OFFSET 0x8000ULL -#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ - MPC8544_PCI_REGS_OFFSET) #define MPC8544_PCI_REGS_SIZE 0x1000ULL -#define MPC8544_PCI_IO 0xE1000000ULL #define MPC8544_UTIL_OFFSET 0xe0000ULL -#define MPC8544_SPIN_BASE 0xEF000000ULL #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL #define MPC8XXX_GPIO_IRQ 43 @@ -298,7 +293,7 @@ static int ppce500_load_device_tree(MachineState *machine, 0x0, 0x20000000, 0x1000000, 0x0, 0x0, - 0x0, 0xe1000000, + params->pci_pio_base >> 32, params->pci_pio_base, 0x0, 0x10000, }; QemuOpts *machine_opts = qemu_get_machine_opts(); @@ -389,7 +384,7 @@ static int ppce500_load_device_tree(MachineState *machine, CPUState *cpu; PowerPCCPU *pcpu; char cpu_name[128]; - uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); + uint64_t cpu_release_addr = params->spin_base + (i * 0x20); cpu = qemu_get_cpu(i); if (cpu == NULL) { @@ -426,7 +421,7 @@ static int ppce500_load_device_tree(MachineState *machine, qemu_fdt_add_subnode(fdt, "/aliases"); /* XXX These should go into their respective devices' code */ - snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); + snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base); qemu_fdt_add_subnode(fdt, soc); qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, @@ -434,7 +429,7 @@ static int ppce500_load_device_tree(MachineState *machine, qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, - MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, + params->ccsrbar_base >> 32, params->ccsrbar_base, MPC8544_CCSRBAR_SIZE); /* XXX should contain a reasonable value */ qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); @@ -493,7 +488,8 @@ static int ppce500_load_device_tree(MachineState *machine, qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); - snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); + snprintf(pci, sizeof(pci), "/pci@%llx", + params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); qemu_fdt_add_subnode(fdt, pci); qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); @@ -512,8 +508,10 @@ static int ppce500_load_device_tree(MachineState *machine, } qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); - qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, - MPC8544_PCI_REGS_BASE, 0, 0x1000); + qemu_fdt_setprop_cells(fdt, pci, "reg", + (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, + (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), + 0, 0x1000); qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); @@ -841,7 +839,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; - env->mpic_iack = MPC8544_CCSRBAR_BASE + + env->mpic_iack = params->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); @@ -875,7 +873,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) qdev_init_nofail(dev); ccsr = CCSR(dev); ccsr_addr_space = &ccsr->ccsr_space; - memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, + memory_region_add_subregion(address_space_mem, params->ccsrbar_base, ccsr_addr_space); mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); @@ -917,7 +915,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) if (!pci_bus) printf("couldn't create PCI controller!\n"); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base); if (pci_bus) { /* Register network interfaces. */ @@ -927,7 +925,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) } /* Register spinning region */ - sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); + sysbus_create_simple("e500-spin", params->spin_base, NULL); if (cur_base < (32 * 1024 * 1024)) { /* u-boot occupies memory up to 32MB, so load blobs above */ diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 9f61ab2..d96f72d 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -17,6 +17,9 @@ typedef struct PPCE500Params { hwaddr platform_bus_size; int platform_bus_first_irq; int platform_bus_num_irqs; + hwaddr ccsrbar_base; + hwaddr pci_pio_base; + hwaddr spin_base; } PPCE500Params; void ppce500_init(MachineState *machine, PPCE500Params *params); diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index d50ae00..1600fcf 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -41,6 +41,9 @@ static void e500plat_init(MachineState *machine) .platform_bus_size = (128ULL * 1024 * 1024), .platform_bus_first_irq = 5, .platform_bus_num_irqs = 10, + .ccsrbar_base = 0xE0000000ULL, + .pci_pio_base = 0xE1000000ULL, + .spin_base = 0xEF000000ULL, }; /* Older KVM versions don't support EPR which breaks guests when we announce diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index b99f74a..f131633 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -33,6 +33,9 @@ static void mpc8544ds_init(MachineState *machine) .pci_nr_slots = 2, .fixup_devtree = mpc8544ds_fixup_devtree, .mpic_version = OPENPIC_MODEL_FSL_MPIC_20, + .ccsrbar_base = 0xE0000000ULL, + .pci_pio_base = 0xE1000000ULL, + .spin_base = 0xEF000000ULL, }; ppce500_init(machine, ¶ms); -- cgit v1.1 From e6b4e5f4795b2591fd91bea671e3e22e08fd0e75 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 7 Nov 2014 17:07:03 +0100 Subject: PPC: e500: Move CCSR and MMIO space to upper end of address space On e500 we're basically guaranteed to have 36bits of physical address space available for our enjoyment. Older chips (like the mpc8544) only had 32bits, but everything from e500v2 onwards bumped it up. It's reasonably safe to assume that if you're using the PV machine, your guest kernel is configured to support 36bit physical address space. So in order to support more guest RAM, we can move CCSR and other MMIO windows right below the end of our 36bit address space, just like later SoC versions of e500 do. With this patch, I'm able to successfully spawn an e500 VM with -m 48G. Signed-off-by: Alexander Graf --- hw/ppc/e500plat.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'hw') diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 1600fcf..1b8a68d 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -41,9 +41,9 @@ static void e500plat_init(MachineState *machine) .platform_bus_size = (128ULL * 1024 * 1024), .platform_bus_first_irq = 5, .platform_bus_num_irqs = 10, - .ccsrbar_base = 0xE0000000ULL, - .pci_pio_base = 0xE1000000ULL, - .spin_base = 0xEF000000ULL, + .ccsrbar_base = 0xFE0000000ULL, + .pci_pio_base = 0xFE1000000ULL, + .spin_base = 0xFEF000000ULL, }; /* Older KVM versions don't support EPR which breaks guests when we announce -- cgit v1.1 From 44045ce9740945056a58ecb53d2af9ae00083632 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 12 Nov 2014 22:35:33 +0100 Subject: PPC: mpc8554ds: Tell user about exceeding RAM limits The mpc8544ds board only supports up to 3GB of RAM due to its limited address space. When the user requests more, abort and tell him that he should use less. Signed-off-by: Alexander Graf --- hw/ppc/mpc8544ds.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'hw') diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index f131633..fb74b3f 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -15,6 +15,7 @@ #include "hw/boards.h" #include "sysemu/device_tree.h" #include "hw/ppc/openpic.h" +#include "qemu/error-report.h" static void mpc8544ds_fixup_devtree(PPCE500Params *params, void *fdt) { @@ -38,6 +39,11 @@ static void mpc8544ds_init(MachineState *machine) .spin_base = 0xEF000000ULL, }; + if (machine->ram_size > 0xc0000000) { + error_report("The MPC8544DS board only supports up to 3GB of RAM"); + exit(1); + } + ppce500_init(machine, ¶ms); } -- cgit v1.1 From cb3778a0455a2e5a48d7ef0ec8dc656313820389 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 12 Nov 2014 22:44:52 +0100 Subject: PPC: e500 pci host: Add support for ATMUs The e500 PCI controller has configurable windows that allow a guest OS to selectively map parts of the PCI bus space to CPU address space and to selectively map parts of the CPU address space for DMA requests into PCI visible address ranges. So far, we've simply assumed that this mapping is 1:1 and ignored it. However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live inside the first 32bits of address space. This means if we always treat all mappings as 1:1, this map will collide with our RAM map from the CPU's point of view. So this patch adds proper ATMU support which allows us to keep the PCICSRBAR below 32bits local to the PCI bus and have another, different window to PCI BARs at the upper end of address space. We leverage this on e500plat though, mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU. With this patch, I can run guests with lots of RAM and not coincidently access MSI-X mappings while I really want to access RAM. Signed-off-by: Alexander Graf --- hw/pci-host/ppce500.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++--- hw/ppc/e500.c | 6 +-- hw/ppc/e500.h | 2 + hw/ppc/e500plat.c | 2 + hw/ppc/mpc8544ds.c | 2 + 5 files changed, 115 insertions(+), 10 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 1b4c0f0..574f8b2 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -62,11 +62,19 @@ #define PPCE500_PCI_NR_POBS 5 #define PPCE500_PCI_NR_PIBS 3 +#define PIWAR_EN 0x80000000 /* Enable */ +#define PIWAR_PF 0x20000000 /* prefetch */ +#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_SZ_MASK 0x0000003f + struct pci_outbound { uint32_t potar; uint32_t potear; uint32_t powbar; uint32_t powar; + MemoryRegion mem; }; struct pci_inbound { @@ -74,6 +82,7 @@ struct pci_inbound { uint32_t piwbar; uint32_t piwbear; uint32_t piwar; + MemoryRegion mem; }; #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" @@ -91,10 +100,13 @@ struct PPCE500PCIState { uint32_t irq_num[PCI_NUM_PINS]; uint32_t first_slot; uint32_t first_pin_irq; + AddressSpace bm_as; + MemoryRegion bm; /* mmio maps */ MemoryRegion container; MemoryRegion iomem; MemoryRegion pio; + MemoryRegion busmem; }; #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" @@ -181,6 +193,71 @@ static uint64_t pci_reg_read4(void *opaque, hwaddr addr, return value; } +/* DMA mapping */ +static void e500_update_piw(PPCE500PCIState *pci, int idx) +{ + uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; + uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; + uint64_t war = pci->pib[idx].piwar; + uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); + MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *mem = &pci->pib[idx].mem; + MemoryRegion *bm = &pci->bm; + char *name; + + if (memory_region_is_mapped(mem)) { + /* Before we modify anything, unmap and destroy the region */ + memory_region_del_subregion(bm, mem); + object_unparent(OBJECT(mem)); + } + + if (!(war & PIWAR_EN)) { + /* Not enabled, nothing to do */ + return; + } + + name = g_strdup_printf("PCI Inbound Window %d", idx); + memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, + size); + memory_region_add_subregion_overlap(bm, wbar, mem, -1); + g_free(name); + + pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n", + __func__, size, wbar, tar); +} + +/* BAR mapping */ +static void e500_update_pow(PPCE500PCIState *pci, int idx) +{ + uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; + uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; + uint64_t war = pci->pob[idx].powar; + uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); + MemoryRegion *mem = &pci->pob[idx].mem; + MemoryRegion *address_space_mem = get_system_memory(); + char *name; + + if (memory_region_is_mapped(mem)) { + /* Before we modify anything, unmap and destroy the region */ + memory_region_del_subregion(address_space_mem, mem); + object_unparent(OBJECT(mem)); + } + + if (!(war & PIWAR_EN)) { + /* Not enabled, nothing to do */ + return; + } + + name = g_strdup_printf("PCI Outbound Window %d", idx); + memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, + size); + memory_region_add_subregion(address_space_mem, wbar, mem); + g_free(name); + + pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n", + __func__, size, wbar, tar); +} + static void pci_reg_write4(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -199,18 +276,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr, case PPCE500_PCI_OW3: case PPCE500_PCI_OW4: idx = (addr >> 5) & 0x7; - switch (addr & 0xC) { + switch (addr & 0x1F) { case PCI_POTAR: pci->pob[idx].potar = value; + e500_update_pow(pci, idx); break; case PCI_POTEAR: pci->pob[idx].potear = value; + e500_update_pow(pci, idx); break; case PCI_POWBAR: pci->pob[idx].powbar = value; + e500_update_pow(pci, idx); break; case PCI_POWAR: pci->pob[idx].powar = value; + e500_update_pow(pci, idx); break; default: break; @@ -221,18 +302,22 @@ static void pci_reg_write4(void *opaque, hwaddr addr, case PPCE500_PCI_IW2: case PPCE500_PCI_IW1: idx = ((addr >> 5) & 0x3) - 1; - switch (addr & 0xC) { + switch (addr & 0x1F) { case PCI_PITAR: pci->pib[idx].pitar = value; + e500_update_piw(pci, idx); break; case PCI_PIWBAR: pci->pib[idx].piwbar = value; + e500_update_piw(pci, idx); break; case PCI_PIWBEAR: pci->pib[idx].piwbear = value; + e500_update_piw(pci, idx); break; case PCI_PIWAR: pci->pib[idx].piwar = value; + e500_update_piw(pci, idx); break; default: break; @@ -349,13 +434,20 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d) return 0; } +static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque, + int devfn) +{ + PPCE500PCIState *s = opaque; + + return &s->bm_as; +} + static int e500_pcihost_initfn(SysBusDevice *dev) { PCIHostState *h; PPCE500PCIState *s; PCIBus *b; int i; - MemoryRegion *address_space_mem = get_system_memory(); h = PCI_HOST_BRIDGE(dev); s = PPC_E500_PCI_HOST_BRIDGE(dev); @@ -369,12 +461,22 @@ static int e500_pcihost_initfn(SysBusDevice *dev) } memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); + memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); + + /* PIO lives at the bottom of our bus space */ + memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2); b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq, - mpc85xx_pci_map_irq, s, address_space_mem, - &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); + mpc85xx_pci_map_irq, s, &s->busmem, &s->pio, + PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); h->bus = b; + /* Set up PCI view of memory */ + memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX); + memory_region_add_subregion(&s->bm, 0x0, &s->busmem); + address_space_init(&s->bm_as, &s->bm, "pci-bm"); + pci_setup_iommu(b, e500_pcihost_set_iommu, s); + pci_create_simple(b, 0, "e500-host-bridge"); memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); @@ -388,7 +490,6 @@ static int e500_pcihost_initfn(SysBusDevice *dev) memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); sysbus_init_mmio(dev, &s->container); - sysbus_init_mmio(dev, &s->pio); pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); return 0; diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 1aaa515..a2e60b4 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -288,8 +288,8 @@ static int ppce500_load_device_tree(MachineState *machine, int len; uint32_t pci_ranges[14] = { - 0x2000000, 0x0, 0xc0000000, - 0x0, 0xc0000000, + 0x2000000, 0x0, params->pci_mmio_bus_base, + params->pci_mmio_base >> 32, params->pci_mmio_base, 0x0, 0x20000000, 0x1000000, 0x0, 0x0, @@ -915,8 +915,6 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) if (!pci_bus) printf("couldn't create PCI controller!\n"); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base); - if (pci_bus) { /* Register network interfaces. */ for (i = 0; i < nb_nics; i++) { diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index d96f72d..ef224ea 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -19,6 +19,8 @@ typedef struct PPCE500Params { int platform_bus_num_irqs; hwaddr ccsrbar_base; hwaddr pci_pio_base; + hwaddr pci_mmio_base; + hwaddr pci_mmio_bus_base; hwaddr spin_base; } PPCE500Params; diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 1b8a68d..14b14ea 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -43,6 +43,8 @@ static void e500plat_init(MachineState *machine) .platform_bus_num_irqs = 10, .ccsrbar_base = 0xFE0000000ULL, .pci_pio_base = 0xFE1000000ULL, + .pci_mmio_base = 0xC00000000ULL, + .pci_mmio_bus_base = 0xE0000000ULL, .spin_base = 0xFEF000000ULL, }; diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index fb74b3f..3a3b141 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -35,6 +35,8 @@ static void mpc8544ds_init(MachineState *machine) .fixup_devtree = mpc8544ds_fixup_devtree, .mpic_version = OPENPIC_MODEL_FSL_MPIC_20, .ccsrbar_base = 0xE0000000ULL, + .pci_mmio_base = 0xC0000000ULL, + .pci_mmio_bus_base = 0xC0000000ULL, .pci_pio_base = 0xE1000000ULL, .spin_base = 0xEF000000ULL, }; -- cgit v1.1 From 01a579729b2e614bd02b25c8504976eeecb64eff Mon Sep 17 00:00:00 2001 From: Samuel Mendoza-Jonas Date: Mon, 17 Nov 2014 15:12:28 +1100 Subject: spapr: Fix stale HTAB during live migration (KVM) If a guest reboots during a running migration, changes to the hash page table are not necessarily updated on the destination. Opening a new file descriptor to the HTAB forces the migration handler to resend the entire table. Signed-off-by: Samuel Mendoza-Jonas Reviewed-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- hw/ppc/spapr.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'hw') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 08401e0..869b721 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -833,6 +833,11 @@ static void spapr_reset_htab(sPAPREnvironment *spapr) /* Kernel handles htab, we don't need to allocate one */ spapr->htab_shift = shift; kvmppc_kern_htab = true; + + /* Tell readers to update their file descriptor */ + if (spapr->htab_fd >= 0) { + spapr->htab_fd_stale = true; + } } else { if (!spapr->htab) { /* Allocate an htab if we don't yet have one */ @@ -867,6 +872,28 @@ static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) return 0; } +/* + * A guest reset will cause spapr->htab_fd to become stale if being used. + * Reopen the file descriptor to make sure the whole HTAB is properly read. + */ +static int spapr_check_htab_fd(sPAPREnvironment *spapr) +{ + int rc = 0; + + if (spapr->htab_fd_stale) { + close(spapr->htab_fd); + spapr->htab_fd = kvmppc_get_htab_fd(false); + if (spapr->htab_fd < 0) { + error_report("Unable to open fd for reading hash table from KVM: " + "%s", strerror(errno)); + rc = -1; + } + spapr->htab_fd_stale = false; + } + + return rc; +} + static void ppc_spapr_reset(void) { PowerPCCPU *first_ppc_cpu; @@ -1005,6 +1032,7 @@ static int htab_save_setup(QEMUFile *f, void *opaque) assert(kvm_enabled()); spapr->htab_fd = kvmppc_get_htab_fd(false); + spapr->htab_fd_stale = false; if (spapr->htab_fd < 0) { fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", strerror(errno)); @@ -1157,6 +1185,11 @@ static int htab_save_iterate(QEMUFile *f, void *opaque) if (!spapr->htab) { assert(kvm_enabled()); + rc = spapr_check_htab_fd(spapr); + if (rc < 0) { + return rc; + } + rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); if (rc < 0) { @@ -1188,6 +1221,11 @@ static int htab_save_complete(QEMUFile *f, void *opaque) assert(kvm_enabled()); + rc = spapr_check_htab_fd(spapr); + if (rc < 0) { + return rc; + } + rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); if (rc < 0) { return rc; -- cgit v1.1 From 338c25b6929b5436a42aaa106c7e9136cf1ff4dc Mon Sep 17 00:00:00 2001 From: Samuel Mendoza-Jonas Date: Mon, 17 Nov 2014 15:12:29 +1100 Subject: spapr: Fix integer overflow during migration (TCG) The n_valid and n_invalid fields are unsigned short integers but it is possible to have more than 65535 entries in a contiguous hunk, overflowing the field. This results in an incorrect HTAB being sent to the destination during migration. Signed-off-by: Samuel Mendoza-Jonas Reviewed-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- hw/ppc/spapr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'hw') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 869b721..765a44c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1065,7 +1065,7 @@ static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, /* Consume valid HPTEs */ chunkstart = index; - while ((index < htabslots) + while ((index < htabslots) && (index - chunkstart < USHRT_MAX) && HPTE_VALID(HPTE(spapr->htab, index))) { index++; CLEAN_HPTE(HPTE(spapr->htab, index)); @@ -1117,7 +1117,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, chunkstart = index; /* Consume valid dirty HPTEs */ - while ((index < htabslots) + while ((index < htabslots) && (index - chunkstart < USHRT_MAX) && HPTE_DIRTY(HPTE(spapr->htab, index)) && HPTE_VALID(HPTE(spapr->htab, index))) { CLEAN_HPTE(HPTE(spapr->htab, index)); @@ -1127,7 +1127,7 @@ static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, invalidstart = index; /* Consume invalid dirty HPTEs */ - while ((index < htabslots) + while ((index < htabslots) && (index - invalidstart < USHRT_MAX) && HPTE_DIRTY(HPTE(spapr->htab, index)) && !HPTE_VALID(HPTE(spapr->htab, index))) { CLEAN_HPTE(HPTE(spapr->htab, index)); -- cgit v1.1 From e6b8fd246c19701b05f5b65a56b0cc91bbd05ac6 Mon Sep 17 00:00:00 2001 From: Samuel Mendoza-Jonas Date: Mon, 17 Nov 2014 15:12:30 +1100 Subject: spapr: Fix stale HTAB during live migration (TCG) If a TCG guest reboots during a running migration HTAB entries are not marked dirty, and the destination boots with an invalid HTAB. When a reboot occurs, explicitly mark the current HTAB dirty after clearing it. Signed-off-by: Samuel Mendoza-Jonas Reviewed-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- hw/ppc/spapr.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'hw') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 765a44c..720aab5 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -819,9 +819,16 @@ static void emulate_spapr_hypercall(PowerPCCPU *cpu) } } +#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) +#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) +#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) +#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) +#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) + static void spapr_reset_htab(sPAPREnvironment *spapr) { long shift; + int index; /* allocate hash page table. For now we always make this 16mb, * later we should probably make it scale to the size of guest @@ -846,6 +853,10 @@ static void spapr_reset_htab(sPAPREnvironment *spapr) /* And clear it */ memset(spapr->htab, 0, HTAB_SIZE(spapr)); + + for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { + DIRTY_HPTE(HPTE(spapr->htab, index)); + } } /* Update the RMA size if necessary */ @@ -1013,11 +1024,6 @@ static const VMStateDescription vmstate_spapr = { }, }; -#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) -#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) -#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) -#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) - static int htab_save_setup(QEMUFile *f, void *opaque) { sPAPREnvironment *spapr = opaque; -- cgit v1.1 From 77bad151fbd2b2eed1e959ecc2c3f2ee2f080f6c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 26 Nov 2014 15:01:01 +0100 Subject: ppc: do not use get_clock_realtime() Use the external qemu-timer API instead. Signed-off-by: Paolo Bonzini Signed-off-by: Alexander Graf --- hw/ppc/ppc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index bec82cd..5ce565d 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -844,7 +844,7 @@ static void timebase_pre_save(void *opaque) return; } - tb->time_of_the_day_ns = get_clock_realtime(); + tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); /* * tb_offset is only expected to be changed by migration so * there is no need to update it from KVM here @@ -873,7 +873,7 @@ static int timebase_post_load(void *opaque, int version_id) * We try to adjust timebase by downtime if host clocks are not * too much out of sync (1 second for now). */ - host_ns = get_clock_realtime(); + host_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); ns_diff = MAX(0, host_ns - tb_remote->time_of_the_day_ns); migration_duration_ns = MIN(NSEC_PER_SEC, ns_diff); migration_duration_tb = muldiv64(migration_duration_ns, freq, NSEC_PER_SEC); -- cgit v1.1 From 5f9490de566c5b092a6cfedc3c7a37a9c9dee917 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 8 Dec 2014 13:48:02 +1100 Subject: PPC: Fix crash on spapr_tce_table_finalize() spapr_tce_table_finalize() can SEGV if the object was not previously realized. In particular this can be triggered by running qemu-system-ppc -device spapr-tce-table,? The basic problem is that we have mismatched initialization versus finalization: spapr_tce_table_finalize() is attempting to undo things that are done in spapr_tce_table_realize(), not an instance_init function. Therefore, replace spapr_tce_table_finalize() with spapr_tce_table_unrealize(). Signed-off-by: David Gibson Cc: qemu-stable@nongnu.org Signed-off-by: Alexander Graf --- hw/ppc/spapr_iommu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'hw') diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 6c91d8e..da47474 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -173,9 +173,9 @@ sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn, return tcet; } -static void spapr_tce_table_finalize(Object *obj) +static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) { - sPAPRTCETable *tcet = SPAPR_TCE_TABLE(obj); + sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); QLIST_REMOVE(tcet, list); @@ -420,6 +420,7 @@ static void spapr_tce_table_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->init = spapr_tce_table_realize; dc->reset = spapr_tce_reset; + dc->unrealize = spapr_tce_table_unrealize; QLIST_INIT(&spapr_tce_tables); @@ -435,7 +436,6 @@ static TypeInfo spapr_tce_table_info = { .parent = TYPE_DEVICE, .instance_size = sizeof(sPAPRTCETable), .class_init = spapr_tce_table_class_init, - .instance_finalize = spapr_tce_table_finalize, }; static void register_types(void) -- cgit v1.1 From 82e345f57e6482cef960677613125c5aaf2b1654 Mon Sep 17 00:00:00 2001 From: Amit Tomar Date: Fri, 19 Dec 2014 14:20:37 +0000 Subject: PPC: e500: Fix GPIO controller interrupt number The GPIO controller lives at IRQ 47, not 43 on real hardware. This is a problem because IRQ 43 is occupied by the I2C controller which we want to implement next, so we'd have a conflict on that IRQ number. Move the GPIO controller to IRQ 47 where it belongs. Signed-off-by: Amit Singh Tomar Signed-off-by: Alexander Graf --- hw/ppc/e500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index a2e60b4..7e17d18 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -60,7 +60,7 @@ #define MPC8544_PCI_REGS_SIZE 0x1000ULL #define MPC8544_UTIL_OFFSET 0xe0000ULL #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL -#define MPC8XXX_GPIO_IRQ 43 +#define MPC8XXX_GPIO_IRQ 47 struct boot_info { -- cgit v1.1 From 2f285bdd54bb2ff25a213b3b77e9bf46f4306320 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 23 Dec 2014 22:22:16 +0000 Subject: target-ppc: Cast ssize_t to size_t before printing with %zx The mingw32 compiler complains about trying to print variables of type ssize_t with the %z format string specifier. Since we're printing it as unsigned hex anyway, cast to size_t to silence the warning. Signed-off-by: Peter Maydell Signed-off-by: Alexander Graf --- hw/ppc/spapr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 720aab5..2850624 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1482,7 +1482,7 @@ static void ppc_spapr_init(MachineState *machine) } if (spapr->rtas_size > RTAS_MAX_SIZE) { hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", - spapr->rtas_size, RTAS_MAX_SIZE); + (size_t)spapr->rtas_size, RTAS_MAX_SIZE); exit(1); } g_free(filename); -- cgit v1.1 From c760dbb9dc4dfceeb5d4ae07876b10da58d4c630 Mon Sep 17 00:00:00 2001 From: Marcel Apfelbaum Date: Tue, 6 Jan 2015 15:29:12 +0200 Subject: hw/ppc: modified the condition for usb controllers to be created for some ppc machines Some ppc machines create a default usb controller based on a 'machine condition'. Until now the logic was: create the usb controller if: - the usb option was supplied in cli and value is true or - the usb option was absent and both set_defaults and the machine condition were true. Modified the logic to: Create the usb controller if: - the machine condition is true and defaults are enabled or - the usb option is supplied and true. The main for this is to simplify the usb_enabled method. Signed-off-by: Marcel Apfelbaum Reviewed-by: Paolo Bonzini Reviewed-by: Stefan Hajnoczi Signed-off-by: Alexander Graf --- hw/ppc/mac_newworld.c | 3 ++- hw/ppc/spapr.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index b60a832..8ba9499 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -417,7 +417,8 @@ static void ppc_core99_init(MachineState *machine) dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); qdev_init_nofail(dev); - if (usb_enabled(machine_arch == ARCH_MAC99_U3)) { + if ((machine_arch == ARCH_MAC99_U3 && defaults_enabled()) || + usb_enabled(false)) { pci_create_simple(pci_bus, -1, "pci-ohci"); /* U3 needs to use USB for input because Linux doesn't support via-cuda on PPC64 */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 2850624..2b2cc0c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1530,7 +1530,7 @@ static void ppc_spapr_init(MachineState *machine) spapr->has_graphics = true; } - if (usb_enabled(spapr->has_graphics)) { + if ((spapr->has_graphics && defaults_enabled()) || usb_enabled(false)) { pci_create_simple(phb->bus, -1, "pci-ohci"); if (spapr->has_graphics) { usbdevice_create("keyboard"); -- cgit v1.1 From 759bf45d81a892c359fa1a3848c36dcd74b6a42b Mon Sep 17 00:00:00 2001 From: Marcel Apfelbaum Date: Tue, 6 Jan 2015 15:29:13 +0200 Subject: hw/machine: added machine_usb wrapper Following QOM convention, object properties should not be accessed directly. Signed-off-by: Marcel Apfelbaum Reviewed-by: Paolo Bonzini Reviewed-by: Stefan Hajnoczi Signed-off-by: Alexander Graf --- hw/core/machine.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'hw') diff --git a/hw/core/machine.c b/hw/core/machine.c index a0ae5f9..fbd91be 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -398,6 +398,11 @@ static void machine_finalize(Object *obj) g_free(ms->firmware); } +bool machine_usb(MachineState *machine) +{ + return machine->usb; +} + static const TypeInfo machine_info = { .name = TYPE_MACHINE, .parent = TYPE_OBJECT, -- cgit v1.1 From 09f28e5b51e0fb822021efd8396057c818927775 Mon Sep 17 00:00:00 2001 From: Marcel Apfelbaum Date: Tue, 6 Jan 2015 15:29:14 +0200 Subject: hw/usb: simplified usb_enabled The argument is not longer used and the implementation uses now QOM instead of QemuOpts. Signed-off-by: Marcel Apfelbaum Reviewed-by: Stefan Hajnoczi Reviewed-by: Paolo Bonzini Signed-off-by: Alexander Graf --- hw/arm/nseries.c | 2 +- hw/arm/pxa2xx.c | 4 ++-- hw/arm/realview.c | 2 +- hw/arm/versatilepb.c | 2 +- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- hw/ppc/mac_newworld.c | 2 +- hw/ppc/mac_oldworld.c | 2 +- hw/ppc/prep.c | 2 +- hw/ppc/spapr.c | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index c7ebaa6..4d7be5e 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -1344,7 +1344,7 @@ static void n8x0_init(MachineState *machine, n8x0_dss_setup(s); n8x0_cbus_setup(s); n8x0_uart_setup(s); - if (usb_enabled(false)) { + if (usb_enabled()) { n8x0_usb_setup(s); } diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 8967cc4..165ba2a 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -2143,7 +2143,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); } - if (usb_enabled(false)) { + if (usb_enabled()) { sysbus_create_simple("sysbus-ohci", 0x4c000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); } @@ -2276,7 +2276,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); } - if (usb_enabled(false)) { + if (usb_enabled()) { sysbus_create_simple("sysbus-ohci", 0x4c000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); } diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 66e51ef..50cb93d 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -261,7 +261,7 @@ static void realview_init(MachineState *machine, sysbus_connect_irq(busdev, 2, pic[50]); sysbus_connect_irq(busdev, 3, pic[51]); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); - if (usb_enabled(false)) { + if (usb_enabled()) { pci_create_simple(pci_bus, -1, "pci-ohci"); } n = drive_get_max_bus(IF_SCSI); diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 6c4c2e7..b1dae77 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -281,7 +281,7 @@ static void versatile_init(MachineState *machine, int board_id) pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); } } - if (usb_enabled(false)) { + if (usb_enabled()) { pci_create_simple(pci_bus, -1, "pci-ohci"); } n = drive_get_max_bus(IF_SCSI); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 220f741..f0a3201 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -274,7 +274,7 @@ static void pc_init1(MachineState *machine, pc_cmos_init(below_4g_mem_size, above_4g_mem_size, machine->boot_order, machine, floppy, idebus[0], idebus[1], rtc_state); - if (pci_enabled && usb_enabled(false)) { + if (pci_enabled && usb_enabled()) { pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci"); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 7ba0535..a432944 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -265,7 +265,7 @@ static void pc_q35_init(MachineState *machine) ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); ahci_ide_create_devs(ahci, hd); - if (usb_enabled(false)) { + if (usb_enabled()) { /* Should we create 6 UHCI according to ich9 spec? */ ehci_create_ich9_with_companions(host_bus, 0x1d); } diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 8ba9499..ed37d6b 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -418,7 +418,7 @@ static void ppc_core99_init(MachineState *machine) qdev_init_nofail(dev); if ((machine_arch == ARCH_MAC99_U3 && defaults_enabled()) || - usb_enabled(false)) { + usb_enabled()) { pci_create_simple(pci_bus, -1, "pci-ohci"); /* U3 needs to use USB for input because Linux doesn't support via-cuda on PPC64 */ diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index c7224d7..3079510 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -304,7 +304,7 @@ static void ppc_heathrow_init(MachineState *machine) dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); qdev_init_nofail(dev); - if (usb_enabled(false)) { + if (usb_enabled()) { pci_create_simple(pci_bus, -1, "pci-ohci"); } diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index dd8433d..15df7f3 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -539,7 +539,7 @@ static void ppc_prep_init(MachineState *machine) memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); #endif - if (usb_enabled(false)) { + if (usb_enabled()) { pci_create_simple(pci_bus, -1, "pci-ohci"); } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 2b2cc0c..d2b8b12 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1530,7 +1530,7 @@ static void ppc_spapr_init(MachineState *machine) spapr->has_graphics = true; } - if ((spapr->has_graphics && defaults_enabled()) || usb_enabled(false)) { + if ((spapr->has_graphics && defaults_enabled()) || usb_enabled()) { pci_create_simple(phb->bus, -1, "pci-ohci"); if (spapr->has_graphics) { usbdevice_create("keyboard"); -- cgit v1.1 From b8cbc738de38f2a669de9920fc0b0ee14c1d2dd8 Mon Sep 17 00:00:00 2001 From: Marcel Apfelbaum Date: Tue, 6 Jan 2015 15:29:15 +0200 Subject: hw/ppc/mac_newworld: QOMified mac99 machines Signed-off-by: Marcel Apfelbaum Reviewed-by: Stefan Hajnoczi Reviewed-by: Paolo Bonzini Signed-off-by: Alexander Graf --- hw/ppc/mac_newworld.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) (limited to 'hw') diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index ed37d6b..b54f94a 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -502,18 +502,27 @@ static int core99_kvm_type(const char *arg) return 2; } -static QEMUMachine core99_machine = { - .name = "mac99", - .desc = "Mac99 based PowerMAC", - .init = ppc_core99_init, - .max_cpus = MAX_CPUS, - .default_boot_order = "cd", - .kvm_type = core99_kvm_type, +static void core99_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->name = "mac99"; + mc->desc = "Mac99 based PowerMAC"; + mc->init = ppc_core99_init; + mc->max_cpus = MAX_CPUS; + mc->default_boot_order = "cd"; + mc->kvm_type = core99_kvm_type; +} + +static const TypeInfo core99_machine_info = { + .name = "mac99-machine", + .parent = TYPE_MACHINE, + .class_init = core99_machine_class_init, }; -static void core99_machine_init(void) +static void mac_machine_register_types(void) { - qemu_register_machine(&core99_machine); + type_register_static(&core99_machine_info); } -machine_init(core99_machine_init); +type_init(mac_machine_register_types) -- cgit v1.1 From 4ee9ced979e68522ee38ea759e7630ac70f15fa8 Mon Sep 17 00:00:00 2001 From: Marcel Apfelbaum Date: Tue, 6 Jan 2015 15:29:16 +0200 Subject: hw/ppc/spapr: simplify usb controller creation logic Signed-off-by: Marcel Apfelbaum Reviewed-by: Stefan Hajnoczi Reviewed-by: Paolo Bonzini Signed-off-by: Alexander Graf --- hw/ppc/spapr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d2b8b12..b560459 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1528,9 +1528,10 @@ static void ppc_spapr_init(MachineState *machine) /* Graphics */ if (spapr_vga_init(phb->bus)) { spapr->has_graphics = true; + machine->usb |= defaults_enabled(); } - if ((spapr->has_graphics && defaults_enabled()) || usb_enabled()) { + if (machine->usb) { pci_create_simple(phb->bus, -1, "pci-ohci"); if (spapr->has_graphics) { usbdevice_create("keyboard"); -- cgit v1.1 From 75c74ccbe1d4175edb79c6f810c2207dcf5edb22 Mon Sep 17 00:00:00 2001 From: Marcel Apfelbaum Date: Tue, 6 Jan 2015 15:29:17 +0200 Subject: hw/ppc/mac_newworld: simplify usb controller creation logic Signed-off-by: Marcel Apfelbaum Reviewed-by: Stefan Hajnoczi Reviewed-by: Paolo Bonzini Signed-off-by: Alexander Graf --- hw/ppc/mac_newworld.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index b54f94a..c377012 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -371,6 +371,7 @@ static void ppc_core99_init(MachineState *machine) /* 970 gets a U3 bus */ pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99_U3; + machine->usb |= defaults_enabled(); } else { pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); machine_arch = ARCH_MAC99; @@ -417,8 +418,7 @@ static void ppc_core99_init(MachineState *machine) dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); qdev_init_nofail(dev); - if ((machine_arch == ARCH_MAC99_U3 && defaults_enabled()) || - usb_enabled()) { + if (machine->usb) { pci_create_simple(pci_bus, -1, "pci-ohci"); /* U3 needs to use USB for input because Linux doesn't support via-cuda on PPC64 */ -- cgit v1.1