From 83234b8289e64fc359a5bf02d886a333d65b8f8c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 17 Dec 2021 17:57:12 +0100 Subject: hw/ppc/mac.h: Remove MAX_CPUS macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mac.h header defines a MAX_CPUS macro. This is confusingly named, because it suggests it's a generic setting, but in fact it's used by only the g3beige and mac99 machines. It's also using a single macro for two values which aren't inherently the same -- if one of these two machines was updated to support SMP configurations then it would want a different max_cpus value to the other. Since the macro is used in only two places, just expand it out and get rid of it. If hypothetical future work to support SMP in these boards needs a compile-time-known limit on the number of CPUs, we can give it a suitable name at that point. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-Id: <20211105184216.120972-1-peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater --- hw/ppc/mac.h | 3 --- hw/ppc/mac_newworld.c | 3 ++- hw/ppc/mac_oldworld.c | 3 ++- 3 files changed, 4 insertions(+), 5 deletions(-) (limited to 'hw') diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 22c8408..a1fa8f8 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -36,9 +36,6 @@ #include "hw/pci-host/uninorth.h" #include "qom/object.h" -/* SMP is not enabled, for now */ -#define MAX_CPUS 1 - #define NVRAM_SIZE 0x2000 #define PROM_FILENAME "openbios-ppc" diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 7bb7ac3..4bddb52 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -581,7 +581,8 @@ static void core99_machine_class_init(ObjectClass *oc, void *data) mc->desc = "Mac99 based PowerMAC"; mc->init = ppc_core99_init; mc->block_default_type = IF_IDE; - mc->max_cpus = MAX_CPUS; + /* SMP is not supported currently */ + mc->max_cpus = 1; mc->default_boot_order = "cd"; mc->default_display = "std"; mc->kvm_type = core99_kvm_type; diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index de2be96..7016979 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -423,7 +423,8 @@ static void heathrow_class_init(ObjectClass *oc, void *data) mc->desc = "Heathrow based PowerMAC"; mc->init = ppc_heathrow_init; mc->block_default_type = IF_IDE; - mc->max_cpus = MAX_CPUS; + /* SMP is not supported currently */ + mc->max_cpus = 1; #ifndef TARGET_PPC64 mc->is_default = true; #endif -- cgit v1.1 From ef80a708b57ddc8f605d9982bfaa0536e720ed9f Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: ivshmem.c: change endianness to LITTLE_ENDIAN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ivshmem device, as with most PCI devices, uses little endian byte order. However, the endianness of its mmio_ops is marked as DEVICE_NATIVE_ENDIAN. This presents not only the usual problems with big endian hosts but also with PowerPC little endian hosts as well, since the Power architecture in QEMU uses big endian hardware (XIVE controller, PCI Host Bridges, etc) even if the host is in little endian byte order. As it is today, the IVPosition of the device will be byte swapped when running in Power BE and LE. This can be seen by changing the existing qtest 'ivshmem-test' to run in ppc64 hosts and printing the IVPOSITION regs in test_ivshmem_server() right after the VM ids assert. For x86_64 the VM id values read are '0' and '1', for ppc64 (tested in a Power8 RHEL 7.9 BE server) and ppc64le (tested in a Power9 RHEL 8.6 LE server) the ids will be '0' and '0x1000000'. Change this device to LITTLE_ENDIAN fixes the issue for Power hosts of both endianness, and every other big-endian architecture that might use this device, without impacting x86 users. Fixes: cb06608e17f8 ("ivshmem: convert to memory API") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/168 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211124092948.335389-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/misc/ivshmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index 1ba4a98..299837e 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -243,7 +243,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, static const MemoryRegionOps ivshmem_mmio_ops = { .read = ivshmem_io_read, .write = ivshmem_io_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, -- cgit v1.1 From fa4b5eaaf923731c8667c3aec7b64ccc3c7757bf Mon Sep 17 00:00:00 2001 From: Christophe Lombard Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: pci-host: Allow extended config space access for PowerNV PHB4 model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PCIe extended configuration space on the device is not currently accessible to the host. if by default, it is still inaccessible for conventional for PCIe buses, add the current flag PCI_BUS_EXTENDED_CONFIG_SPACE on the root bus permits PCI-E extended config space access. Signed-off-by: Christophe Lombard Reviewed-by: Frederic Barrat Reviewed-by: Cédric Le Goater Message-Id: <20211109145053.43524-1-clombard@linux.vnet.ibm.com> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 5c375a9..40b7932 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1205,6 +1205,7 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) &phb->pci_mmio, &phb->pci_io, 0, 4, TYPE_PNV_PHB4_ROOT_BUS); pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); + pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; /* Add a single Root port */ qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id); -- cgit v1.1 From ebe6c3fab8614a26130f7c72dd35ecede11a0f71 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: ppc/pnv.c: add a friendly warning when accel=kvm is used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If one tries to use -machine powernv9,accel=kvm in a Power9 host, a cryptic error will be shown: qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only "-cpu host" is possible qemu-system-ppc64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument Appending '-cpu host' will throw another error: qemu-system-ppc64: invalid chip model 'host' for powernv9 machine The root cause is that in IBM PowerPC we have different specs for the bare-metal and the guests. The bare-metal follows OPAL, the guests follow PAPR. The kernel KVM modules presented in the ppc kernels implements PAPR. This means that we can't use KVM accel when using the powernv machine, which is the emulation of the bare-metal host. All that said, let's give a more informative error in this case. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson Message-Id: <20211130133153.444601-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 71e4551..e5b87e8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -742,6 +742,11 @@ static void pnv_init(MachineState *machine) DriveInfo *pnor = drive_get(IF_MTD, 0, 0); DeviceState *dev; + if (kvm_enabled()) { + error_report("The powernv machine does not work with KVM acceleration"); + exit(EXIT_FAILURE); + } + /* allocate RAM */ if (machine->ram_size < mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); -- cgit v1.1 From bbfbbff5fc0fb4cee42ed22c4430cc5d68bacc27 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: ppc/pnv.c: fix "system-id" FDT when -uuid is set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting -uuid in the pnv machine does not work: ./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid 7ff61ca1-a4a0-4bc1-944c-abd114a35e80 qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt, "system-id", buf)): FDT_ERR_BADSTATE This happens because we're using fdt_property_string(), which is a sequential write function that is supposed to be used when we're building a new FDT, in a case where read/writing into an existing FDT. Fix it by using fdt_setprop_string() instead. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211207094858.744386-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e5b87e8..44ae41a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -522,7 +522,7 @@ static void *pnv_dt_create(MachineState *machine) buf = qemu_uuid_unparse_strdup(&qemu_uuid); _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); if (qemu_uuid_set) { - _FDT((fdt_property_string(fdt, "system-id", buf))); + _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); } g_free(buf); -- cgit v1.1 From 82f64c2384507477618db75d24c92b7324ff674c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Change kernel load address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The default addresses to load the kernel, fdt, initrd of AMCC boards in U-Boot v2015.10 are : "kernel_addr_r=1000000\0" "fdt_addr_r=1800000\0" "ramdisk_addr_r=1900000\0" The taihu is one of these boards, the ref405ep is not but we don't have much information on it and both boards have a very similar address space layout. Also, if loaded at address 0, U-Boot will partially overwrite the uImage because of a bug in get_ram_size() (U-Boot v2015.10) not restoring properly the probed RAM contents and because the exception vectors are installed in the same range. Finally, a gzipped kernel image will be uncompressed at 0x0. These are all good reasons for not mappping a kernel image at this address. Change the kernel load address to match U-Boot expectations and fix loading. Cc: Christophe Leroy Signed-off-by: Cédric Le Goater Reviewed-by: Thomas Huth Message-Id: <20211202191446.1292125-1-clg@kaod.org> Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-2-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 972a7a4..b4249f4 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -45,7 +45,7 @@ #define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_SIZE (2 * MiB) -#define KERNEL_LOAD_ADDR 0x00000000 +#define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 #define USE_FLASH_BIOS -- cgit v1.1 From 26e8bed611222c4e2b9408a8d5a405158e491a98 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc: Mark the 'taihu' machine as deprecated MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar, except for some external periphery. However, the periphery of the 'taihu' machine is hardly emulated at all (e.g. neither the LCD nor the USB part had been implemented), so there is not much value added by this board. The users can use the 'ref405ep' machine to test their PPC405 code instead. Signed-off-by: Thomas Huth Reviewed-by: Daniel Henrique Barboza Message-Id: <20211203164904.290954-2-thuth@redhat.com> Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-3-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index b4249f4..f1623aa 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -547,6 +547,7 @@ static void taihu_class_init(ObjectClass *oc, void *data) mc->init = taihu_405ep_init; mc->default_ram_size = 0x08000000; mc->default_ram_id = "taihu_405ep.ram"; + mc->deprecation_reason = "incomplete, use 'ref405ep' instead"; } static const TypeInfo taihu_type = { -- cgit v1.1 From de82dabeadd0511a3b18c76dc3c666a63798f8ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc: Add trace-events for DCR accesses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-4-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc.c | 2 ++ hw/ppc/trace-events | 3 +++ 2 files changed, 5 insertions(+) (limited to 'hw') diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index e812759..818d757 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1367,6 +1367,7 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) if (dcr->dcr_read == NULL) goto error; *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); + trace_ppc_dcr_read(dcrn, *valp); return 0; @@ -1386,6 +1387,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) dcr = &dcr_env->dcrn[dcrn]; if (dcr->dcr_write == NULL) goto error; + trace_ppc_dcr_write(dcrn, val); (*dcr->dcr_write)(dcr->opaque, dcrn, val); return 0; diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 3bf43fa..602adb8 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -119,6 +119,9 @@ ppc_irq_set_state(const char *name, uint32_t level) "\"%s\" level %d" ppc_irq_reset(const char *name) "%s" ppc_irq_cpu(const char *action) "%s" +ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" +ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" + # prep_systemio.c prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x" prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x" -- cgit v1.1 From 09960a5be3ec4b8caddb894ad5b73d4533ead5fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Convert printfs to trace-events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit and one error message to a LOG_GUEST_ERROR. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-5-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_uc.c | 159 ++++++++++++++++++---------------------------------- hw/ppc/trace-events | 20 +++++++ 2 files changed, 74 insertions(+), 105 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e632c40..e14d61e 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/ppc/ppc.h" #include "hw/i2c/ppc4xx_i2c.h" @@ -38,15 +39,7 @@ #include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" #include "qapi/error.h" - -//#define DEBUG_OPBA -//#define DEBUG_SDRAM -//#define DEBUG_GPIO -//#define DEBUG_SERIAL -//#define DEBUG_OCM -//#define DEBUG_GPT -//#define DEBUG_CLOCKS -//#define DEBUG_CLOCKS_LL +#include "trace.h" ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) @@ -287,13 +280,9 @@ struct ppc4xx_opba_t { static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_opba_t *opba; + ppc4xx_opba_t *opba = opaque; uint32_t ret; -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - opba = opaque; switch (addr) { case 0x00: ret = opba->cr; @@ -306,19 +295,17 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) break; } + trace_opba_readb(addr, ret); return ret; } static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_opba_t *opba; + ppc4xx_opba_t *opba = opaque; + + trace_opba_writeb(addr, value); -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba = opaque; switch (addr) { case 0x00: opba->cr = value & 0xF8; @@ -353,10 +340,9 @@ static void ppc4xx_opba_init(hwaddr base) { ppc4xx_opba_t *opba; + trace_opba_init(base); + opba = g_malloc0(sizeof(ppc4xx_opba_t)); -#ifdef DEBUG_OPBA - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); memory_region_add_subregion(get_system_memory(), base, &opba->io); qemu_register_reset(ppc4xx_opba_reset, opba); @@ -707,20 +693,14 @@ struct ppc405_gpio_t { static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); -#endif - + trace_ppc405_gpio_read(addr, size); return 0; } static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", - __func__, addr, size, value); -#endif + trace_ppc405_gpio_write(addr, size, value); } static const MemoryRegionOps ppc405_gpio_ops = { @@ -737,10 +717,9 @@ static void ppc405_gpio_init(hwaddr base) { ppc405_gpio_t *gpio; + trace_ppc405_gpio_init(base); + gpio = g_malloc0(sizeof(ppc405_gpio_t)); -#ifdef DEBUG_GPIO - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); memory_region_add_subregion(get_system_memory(), base, &gpio->io); qemu_register_reset(&ppc405_gpio_reset, gpio); @@ -770,25 +749,19 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl) { -#ifdef DEBUG_OCM - printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 - " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 - " (%08" PRIx32 " %08" PRIx32 ")\n", - isarc, isacntl, dsarc, dsacntl, - ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); -#endif + trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, + ocm->isacntl, ocm->dsarc, ocm->dsacntl); + if (ocm->isarc != isarc || (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { if (ocm->isacntl & 0x80000000) { /* Unmap previously assigned memory region */ - printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); + trace_ocm_unmap("ISA", ocm->isarc); memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); } if (isacntl & 0x80000000) { /* Map new instruction memory region */ -#ifdef DEBUG_OCM - printf("OCM map ISA %08" PRIx32 "\n", isarc); -#endif + trace_ocm_map("ISA", isarc); memory_region_add_subregion(get_system_memory(), isarc, &ocm->isarc_ram); } @@ -799,9 +772,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, /* Beware not to unmap the region we just mapped */ if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { /* Unmap previously assigned memory region */ -#ifdef DEBUG_OCM - printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); -#endif + trace_ocm_unmap("DSA", ocm->dsarc); memory_region_del_subregion(get_system_memory(), &ocm->dsarc_ram); } @@ -810,9 +781,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, /* Beware not to remap the region we just mapped */ if (!(isacntl & 0x80000000) || dsarc != isarc) { /* Map new data memory region */ -#ifdef DEBUG_OCM - printf("OCM map DSA %08" PRIx32 "\n", dsarc); -#endif + trace_ocm_map("DSA", dsarc); memory_region_add_subregion(get_system_memory(), dsarc, &ocm->dsarc_ram); } @@ -988,14 +957,12 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_gpt_t *gpt; + ppc4xx_gpt_t *gpt = opaque; uint32_t ret; int idx; -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - gpt = opaque; + trace_ppc4xx_gpt_read(addr, size); + switch (addr) { case 0x00: /* Time base counter */ @@ -1044,14 +1011,11 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_gpt_t *gpt; + ppc4xx_gpt_t *gpt = opaque; int idx; -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - gpt = opaque; + trace_ppc4xx_gpt_write(addr, size, value); + switch (addr) { case 0x00: /* Time base counter */ @@ -1144,14 +1108,13 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) ppc4xx_gpt_t *gpt; int i; + trace_ppc4xx_gpt_init(base); + gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); for (i = 0; i < 5; i++) { gpt->irqs[i] = irqs[i]; } gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); -#ifdef DEBUG_GPT - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); qemu_register_reset(ppc4xx_gpt_reset, gpt); @@ -1215,17 +1178,14 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) VCO_out = 0; if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ -#ifdef DEBUG_CLOCKS_LL - printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); -#endif + trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ -#ifdef DEBUG_CLOCKS_LL - printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); -#endif + trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); VCO_out = (uint64_t)cpc->sysclk * M * D; if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { /* Error - unlock the PLL */ - printf("VCO out of range %" PRIu64 "\n", VCO_out); + qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", + VCO_out); #if 0 cpc->pllmr[1] &= ~0x80000000; goto pll_bypass; @@ -1246,54 +1206,43 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) } /* Now, compute all other clocks */ D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ -#ifdef DEBUG_CLOCKS_LL - printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); CPU_clk = PLL_out / D; D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ -#ifdef DEBUG_CLOCKS_LL - printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); PLB_clk = CPU_clk / D; D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); OPB_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); EBC_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); MAL_clk = PLB_clk / D; D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); PCI_clk = PLB_clk / D; D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ -#ifdef DEBUG_CLOCKS_LL - printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); -#endif + trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); UART0_clk = PLL_out / D; D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ -#ifdef DEBUG_CLOCKS_LL - printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); -#endif + trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); UART1_clk = PLL_out / D; -#ifdef DEBUG_CLOCKS - printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 - " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); - printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 - " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 - " UART1 %" PRIu32 "\n", - CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, - UART0_clk, UART1_clk); -#endif + + if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { + g_autofree char *trace = g_strdup_printf( + "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 + " PLL out %" PRIu64 " Hz\n" + "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 + " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 + " UART1 %" PRIu32 "\n", + cpc->sysclk, VCO_out, PLL_out, + CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, + UART0_clk, UART1_clk); + trace_ppc405ep_clocks_setup(trace); + } + /* Setup CPU clocks */ clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); /* Setup PLB clock */ diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 602adb8..ada6446 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -144,3 +144,23 @@ ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32 + +# ppc405_boards.c +opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 +opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64 +opba_init(uint64_t addr) "offet 0x%" PRIx64 + +ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" +ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64 +ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64 + +ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")" +ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32 +ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32 + +ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" +ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64 +ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64 + +ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d" +ppc405ep_clocks_setup(const char *trace) "%s" -- cgit v1.1 From af9e361512a39f1b9a6b29a838656dbeb8fa7233 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was introduced in commit b8d3f5d12642 ("Add flags to support PowerPC 405 bootinfos variations.") but since its value has always been set to '1'. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-6-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 3 +-- hw/ppc/ppc405_boards.c | 2 +- hw/ppc/ppc405_uc.c | 8 +++----- 3 files changed, 5 insertions(+), 8 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index c58f739..4cb77ac 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -56,8 +56,7 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags); +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index f1623aa..2ac38c8 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -261,7 +261,7 @@ static void ref405ep_init(MachineState *machine) bd.bi_plb_busfreq = 33333333; bd.bi_pci_busfreq = 33333333; bd.bi_opbfreq = 33333333; - bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); + bdloc = ppc405_set_bootinfo(env, &bd); env->gpr[3] = bdloc; kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e14d61e..6806d6b 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -41,8 +41,7 @@ #include "qapi/error.h" #include "trace.h" -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags) +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) { CPUState *cs = env_cpu(env); ram_addr_t bdloc; @@ -81,9 +80,8 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); } n = 0x6A; - if (flags & 0x00000001) { - for (i = 0; i < 6; i++) - stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); + for (i = 0; i < 6; i++) { + stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); } stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); n += 4; -- cgit v1.1 From a3e973e1bfffb2cddfc0763fe90414f8ca3bf531 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Change ppc405ep_init() return value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I will be useful to rework the boot from Linux. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-7-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 6 +++++- hw/ppc/ppc405_uc.c | 4 ++-- 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 4cb77ac..ad5f402 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -61,7 +61,7 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); -CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, +PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 2ac38c8..fcdb6d4 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -145,6 +145,7 @@ static void ref405ep_init(MachineState *machine) const char *initrd_filename = machine->initrd_filename; char *filename; ppc4xx_bd_info_t bd; + PowerPCCPU *cpu; CPUPPCState *env; DeviceState *dev; SysBusDevice *s; @@ -180,8 +181,11 @@ static void ref405ep_init(MachineState *machine) memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); ram_bases[1] = 0x00000000; ram_sizes[1] = 0x00000000; - env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, + + cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); + env = &cpu->env; + /* allocate SRAM */ sram_size = 512 * KiB; memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 6806d6b..4ad8169 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1391,7 +1391,7 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], #endif } -CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, +PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], @@ -1490,5 +1490,5 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); - return env; + return cpu; } -- cgit v1.1 From f61b99d35e31d98f1799cdfdf14ec96093e903a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Add some address space definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-8-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 7 +++++++ hw/ppc/ppc405_boards.c | 16 +++++++--------- 2 files changed, 14 insertions(+), 9 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index ad5f402..ea48c36 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -27,6 +27,13 @@ #include "hw/ppc/ppc4xx.h" +#define PPC405EP_SDRAM_BASE 0x00000000 +#define PPC405EP_NVRAM_BASE 0xF0000000 +#define PPC405EP_FPGA_BASE 0xF0300000 +#define PPC405EP_SRAM_BASE 0xFFF00000 +#define PPC405EP_SRAM_SIZE (512 * KiB) +#define PPC405EP_FLASH_BASE 0xFFF80000 + /* Bootinfo as set-up by u-boot */ typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; struct ppc4xx_bd_info_t { diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index fcdb6d4..60dc81f 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -154,7 +154,6 @@ static void ref405ep_init(MachineState *machine) ram_addr_t bdloc; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); hwaddr ram_bases[2], ram_sizes[2]; - target_ulong sram_size; long bios_size; //int phy_addr = 0; //static int phy_addr = 1; @@ -187,10 +186,9 @@ static void ref405ep_init(MachineState *machine) env = &cpu->env; /* allocate SRAM */ - sram_size = 512 * KiB; - memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, + memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, &error_fatal); - memory_region_add_subregion(sysmem, 0xFFF00000, sram); + memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); /* allocate and load BIOS */ #ifdef USE_FLASH_BIOS dinfo = drive_get(IF_PFLASH, 0, 0); @@ -230,24 +228,24 @@ static void ref405ep_init(MachineState *machine) } } /* Register FPGA */ - ref405ep_fpga_init(sysmem, 0xF0300000); + ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE); /* Register NVRAM */ dev = qdev_new("sysbus-m48t08"); qdev_prop_set_int32(dev, "base-year", 1968); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, 0xF0000000); + sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE); /* Load kernel */ linux_boot = (kernel_filename != NULL); if (linux_boot) { memset(&bd, 0, sizeof(bd)); - bd.bi_memstart = 0x00000000; + bd.bi_memstart = PPC405EP_SDRAM_BASE; bd.bi_memsize = machine->ram_size; bd.bi_flashstart = -bios_size; bd.bi_flashsize = -bios_size; bd.bi_flashoffset = 0; - bd.bi_sramstart = 0xFFF00000; - bd.bi_sramsize = sram_size; + bd.bi_sramstart = PPC405EP_SRAM_BASE; + bd.bi_sramsize = PPC405EP_SRAM_SIZE; bd.bi_bootflags = 0; bd.bi_intfreq = 133333333; bd.bi_busfreq = 33333333; -- cgit v1.1 From 9fb100efa169749da9f148440e3b1005345fb6d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Remove flash support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is currently impossible to find a "ppc405_rom.bin" firmware file or a full flash image for the PPC405EP evalution board. Even if it should be technically possible to recreate such an image, it's unlikely that anyone will do it since the board is obsolete and support in QEMU has been broken for about 10 years. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-9-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 60dc81f..a385e8f 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -161,7 +161,6 @@ static void ref405ep_init(MachineState *machine) long kernel_size, initrd_size; int linux_boot; int len; - DriveInfo *dinfo; MemoryRegion *sysmem = get_system_memory(); DeviceState *uicdev; @@ -189,19 +188,8 @@ static void ref405ep_init(MachineState *machine) memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, &error_fatal); memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); + /* allocate and load BIOS */ -#ifdef USE_FLASH_BIOS - dinfo = drive_get(IF_PFLASH, 0, 0); - if (dinfo) { - bios_size = 8 * MiB; - pflash_cfi02_register((uint32_t)(-bios_size), - "ef405ep.bios", bios_size, - blk_by_legacy_dinfo(dinfo), - 64 * KiB, 1, - 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, - 1); - } else -#endif { bios = g_new(MemoryRegion, 1); memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, -- cgit v1.1 From 13d63de59bf31119f3d47e638a64b27da86e1a5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Rework FW load MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QEMU installs a custom U-Boot in-memory descriptor to share board information with Linux, which means that the QEMU machine was initially designed to support booting Linux directly without using the loaded FW. But, it's not that simple because the CPU still starts at address 0xfffffffc where nothing is currently mapped. Support must have been broken these last years. Since we can not find a "ppc405_rom.bin" firmware file, request one to be specified on the command line. A consequence of this change is that the machine can be booted directly from Linux without any FW being loaded. This is still broken and the CPU start address will be fixed in the next changes. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-10-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 45 ++++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 25 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index a385e8f..cfed43d 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -139,24 +139,19 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) static void ref405ep_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); - const char *bios_name = machine->firmware ?: BIOS_FILENAME; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - char *filename; ppc4xx_bd_info_t bd; PowerPCCPU *cpu; CPUPPCState *env; DeviceState *dev; SysBusDevice *s; - MemoryRegion *bios; MemoryRegion *sram = g_new(MemoryRegion, 1); ram_addr_t bdloc; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); hwaddr ram_bases[2], ram_sizes[2]; - long bios_size; - //int phy_addr = 0; - //static int phy_addr = 1; + long bios_size = -1; target_ulong kernel_base, initrd_base; long kernel_size, initrd_size; int linux_boot; @@ -190,31 +185,31 @@ static void ref405ep_init(MachineState *machine) memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); /* allocate and load BIOS */ - { - bios = g_new(MemoryRegion, 1); + if (machine->firmware) { + MemoryRegion *bios = g_new(MemoryRegion, 1); + g_autofree char *filename; + memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, &error_fatal); - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - if (filename) { - bios_size = load_image_size(filename, - memory_region_get_ram_ptr(bios), - BIOS_SIZE); - g_free(filename); - if (bios_size < 0) { - error_report("Could not load PowerPC BIOS '%s'", bios_name); - exit(1); - } - bios_size = (bios_size + 0xfff) & ~0xfff; - memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); - } else if (!qtest_enabled() || kernel_filename != NULL) { - error_report("Could not load PowerPC BIOS '%s'", bios_name); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); + if (!filename) { + error_report("Could not find firmware '%s'", machine->firmware); + exit(1); + } + + bios_size = load_image_size(filename, + memory_region_get_ram_ptr(bios), + BIOS_SIZE); + if (bios_size < 0) { + error_report("Could not load PowerPC BIOS '%s'", machine->firmware); exit(1); - } else { - /* Avoid an uninitialized variable warning */ - bios_size = -1; } + + bios_size = (bios_size + 0xfff) & ~0xfff; + memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); } + /* Register FPGA */ ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE); /* Register NVRAM */ -- cgit v1.1 From e3931ecab32d993fa89802b3a8af39f3ea957b3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Introduce ppc405_set_default_bootinfo() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This routine is a small helper to cleanup the code. The update of the flash fields were removed because there are not of any use when booting from a Linux kernel image. It should be functionally equivalent. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-11-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 28 +--------------------------- hw/ppc/ppc405_uc.c | 41 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 42 insertions(+), 29 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index ea48c36..6fb8b41 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,7 +63,7 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd); +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index cfed43d..71a652e 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -142,7 +142,6 @@ static void ref405ep_init(MachineState *machine) const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - ppc4xx_bd_info_t bd; PowerPCCPU *cpu; CPUPPCState *env; DeviceState *dev; @@ -221,32 +220,7 @@ static void ref405ep_init(MachineState *machine) /* Load kernel */ linux_boot = (kernel_filename != NULL); if (linux_boot) { - memset(&bd, 0, sizeof(bd)); - bd.bi_memstart = PPC405EP_SDRAM_BASE; - bd.bi_memsize = machine->ram_size; - bd.bi_flashstart = -bios_size; - bd.bi_flashsize = -bios_size; - bd.bi_flashoffset = 0; - bd.bi_sramstart = PPC405EP_SRAM_BASE; - bd.bi_sramsize = PPC405EP_SRAM_SIZE; - bd.bi_bootflags = 0; - bd.bi_intfreq = 133333333; - bd.bi_busfreq = 33333333; - bd.bi_baudrate = 115200; - bd.bi_s_version[0] = 'Q'; - bd.bi_s_version[1] = 'M'; - bd.bi_s_version[2] = 'U'; - bd.bi_s_version[3] = '\0'; - bd.bi_r_version[0] = 'Q'; - bd.bi_r_version[1] = 'E'; - bd.bi_r_version[2] = 'M'; - bd.bi_r_version[3] = 'U'; - bd.bi_r_version[4] = '\0'; - bd.bi_procfreq = 133333333; - bd.bi_plb_busfreq = 33333333; - bd.bi_pci_busfreq = 33333333; - bd.bi_opbfreq = 33333333; - bdloc = ppc405_set_bootinfo(env, &bd); + bdloc = ppc405_set_bootinfo(env, machine->ram_size); env->gpr[3] = bdloc; kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 4ad8169..303af58 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -41,7 +41,35 @@ #include "qapi/error.h" #include "trace.h" -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) +static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, + ram_addr_t ram_size) +{ + memset(bd, 0, sizeof(*bd)); + + bd->bi_memstart = PPC405EP_SDRAM_BASE; + bd->bi_memsize = ram_size; + bd->bi_sramstart = PPC405EP_SRAM_BASE; + bd->bi_sramsize = PPC405EP_SRAM_SIZE; + bd->bi_bootflags = 0; + bd->bi_intfreq = 133333333; + bd->bi_busfreq = 33333333; + bd->bi_baudrate = 115200; + bd->bi_s_version[0] = 'Q'; + bd->bi_s_version[1] = 'M'; + bd->bi_s_version[2] = 'U'; + bd->bi_s_version[3] = '\0'; + bd->bi_r_version[0] = 'Q'; + bd->bi_r_version[1] = 'E'; + bd->bi_r_version[2] = 'M'; + bd->bi_r_version[3] = 'U'; + bd->bi_r_version[4] = '\0'; + bd->bi_procfreq = 133333333; + bd->bi_plb_busfreq = 33333333; + bd->bi_pci_busfreq = 33333333; + bd->bi_opbfreq = 33333333; +} + +static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) { CPUState *cs = env_cpu(env); ram_addr_t bdloc; @@ -93,6 +121,17 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) return bdloc; } +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) +{ + ppc4xx_bd_info_t bd; + + memset(&bd, 0, sizeof(bd)); + + ppc405_set_default_bootinfo(&bd, ram_size); + + return __ppc405_set_bootinfo(env, &bd); +} + /*****************************************************************************/ /* Shared peripherals */ -- cgit v1.1 From 337270b2a5b7e23fd595aaf22a789bf3194887cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Fix boot from kernel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The machine can already boot with kernel and initrd U-boot images if a firmware is loaded first. Adapt and improve the load sequence to let the machine boot directly from a Linux kernel ELF image and a usual initrd image if a firmware image is not provided. For that, install a custom CPU reset handler to setup the registers and to start the CPU from the Linux kernel entry point. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-12-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 145 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 102 insertions(+), 43 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 71a652e..3ae2b36 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -41,6 +41,7 @@ #include "qemu/error-report.h" #include "hw/loader.h" #include "qemu/cutils.h" +#include "elf.h" #define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_SIZE (2 * MiB) @@ -136,25 +137,101 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) qemu_register_reset(&ref405ep_fpga_reset, fpga); } +/* + * CPU reset handler when booting directly from a loaded kernel + */ +static struct boot_info { + uint32_t entry; + uint32_t bdloc; + uint32_t initrd_base; + uint32_t initrd_size; + uint32_t cmdline_base; + uint32_t cmdline_size; +} boot_info; + +static void main_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + struct boot_info *bi = env->load_info; + + cpu_reset(CPU(cpu)); + + /* stack: top of sram */ + env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8; + + /* Tune our boot state */ + env->gpr[3] = bi->bdloc; + env->gpr[4] = bi->initrd_base; + env->gpr[5] = bi->initrd_base + bi->initrd_size; + env->gpr[6] = bi->cmdline_base; + env->gpr[7] = bi->cmdline_size; + + env->nip = bi->entry; +} + +static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + hwaddr boot_entry; + hwaddr kernel_base; + int kernel_size; + hwaddr initrd_base; + int initrd_size; + ram_addr_t bdloc; + int len; + + bdloc = ppc405_set_bootinfo(env, machine->ram_size); + boot_info.bdloc = bdloc; + + kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL, + &boot_entry, &kernel_base, NULL, NULL, + 1, PPC_ELF_MACHINE, 0, 0); + if (kernel_size < 0) { + error_report("Could not load kernel '%s' : %s", + machine->kernel_filename, load_elf_strerror(kernel_size)); + exit(1); + } + boot_info.entry = boot_entry; + + /* load initrd */ + if (machine->initrd_filename) { + initrd_base = INITRD_LOAD_ADDR; + initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, + machine->ram_size - initrd_base); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + machine->initrd_filename); + exit(1); + } + + boot_info.initrd_base = initrd_base; + boot_info.initrd_size = initrd_size; + } + + if (machine->kernel_cmdline) { + len = strlen(machine->kernel_cmdline); + bdloc -= ((len + 255) & ~255); + cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1); + boot_info.cmdline_base = bdloc; + boot_info.cmdline_size = bdloc + len; + } + + /* Install our custom reset handler to start from Linux */ + qemu_register_reset(main_cpu_reset, cpu); + env->load_info = &boot_info; +} + static void ref405ep_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); const char *kernel_filename = machine->kernel_filename; - const char *kernel_cmdline = machine->kernel_cmdline; - const char *initrd_filename = machine->initrd_filename; PowerPCCPU *cpu; - CPUPPCState *env; DeviceState *dev; SysBusDevice *s; MemoryRegion *sram = g_new(MemoryRegion, 1); - ram_addr_t bdloc; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); hwaddr ram_bases[2], ram_sizes[2]; - long bios_size = -1; - target_ulong kernel_base, initrd_base; - long kernel_size, initrd_size; - int linux_boot; - int len; MemoryRegion *sysmem = get_system_memory(); DeviceState *uicdev; @@ -176,7 +253,6 @@ static void ref405ep_init(MachineState *machine) cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); - env = &cpu->env; /* allocate SRAM */ memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, @@ -187,6 +263,7 @@ static void ref405ep_init(MachineState *machine) if (machine->firmware) { MemoryRegion *bios = g_new(MemoryRegion, 1); g_autofree char *filename; + long bios_size; memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, &error_fatal); @@ -217,54 +294,36 @@ static void ref405ep_init(MachineState *machine) s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE); - /* Load kernel */ - linux_boot = (kernel_filename != NULL); - if (linux_boot) { - bdloc = ppc405_set_bootinfo(env, machine->ram_size); - env->gpr[3] = bdloc; + + /* Load kernel and initrd using U-Boot images */ + if (kernel_filename && machine->firmware) { + target_ulong kernel_base, initrd_base; + long kernel_size, initrd_size; + kernel_base = KERNEL_LOAD_ADDR; - /* now we can load the kernel */ kernel_size = load_image_targphys(kernel_filename, kernel_base, machine->ram_size - kernel_base); if (kernel_size < 0) { error_report("could not load kernel '%s'", kernel_filename); exit(1); } - printf("Load kernel size %ld at " TARGET_FMT_lx, - kernel_size, kernel_base); + /* load initrd */ - if (initrd_filename) { + if (machine->initrd_filename) { initrd_base = INITRD_LOAD_ADDR; - initrd_size = load_image_targphys(initrd_filename, initrd_base, + initrd_size = load_image_targphys(machine->initrd_filename, + initrd_base, machine->ram_size - initrd_base); if (initrd_size < 0) { error_report("could not load initial ram disk '%s'", - initrd_filename); + machine->initrd_filename); exit(1); } - } else { - initrd_base = 0; - initrd_size = 0; - } - env->gpr[4] = initrd_base; - env->gpr[5] = initrd_size; - if (kernel_cmdline != NULL) { - len = strlen(kernel_cmdline); - bdloc -= ((len + 255) & ~255); - cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); - env->gpr[6] = bdloc; - env->gpr[7] = bdloc + len; - } else { - env->gpr[6] = 0; - env->gpr[7] = 0; } - env->nip = KERNEL_LOAD_ADDR; - } else { - kernel_base = 0; - kernel_size = 0; - initrd_base = 0; - initrd_size = 0; - bdloc = 0; + + /* Load ELF kernel and rootfs.cpio */ + } else if (kernel_filename && !machine->firmware) { + boot_from_kernel(machine, cpu); } } -- cgit v1.1 From cada9f30d35ccbd613ade00c4986a74a5446aa21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Change default PLL values at reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These values are computed and updated by U-Boot at startup. Use them as defaults to improve direct Linux boot. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-13-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_uc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 303af58..2a1e2d7 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1381,9 +1381,9 @@ static void ppc405ep_cpc_reset (void *opaque) cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ cpc->epctl = 0x00000000; - cpc->pllmr[0] = 0x00011010; - cpc->pllmr[1] = 0x40000000; - cpc->ucr = 0x00000000; + cpc->pllmr[0] = 0x00021002; + cpc->pllmr[1] = 0x80a552be; + cpc->ucr = 0x00004646; cpc->srr = 0x00040000; cpc->pci = 0x00000000; cpc->er = 0x00000000; -- cgit v1.1 From e0caa8e64de2c62dfa00afc176e2dd2b3afe7f19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The board information for the 405EP first appeared in commit 04f20795ac81 ("Move PowerPC 405 specific definitions into a separate file ...") An Ethernet address is a 6 byte number. Fix that. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-14-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 6fb8b41..83f156f 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -57,7 +57,7 @@ struct ppc4xx_bd_info_t { uint32_t bi_plb_busfreq; uint32_t bi_pci_busfreq; uint8_t bi_pci_enetaddr[6]; - uint32_t bi_pci_enetaddr2[6]; + uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ uint32_t bi_opbfreq; uint32_t bi_iic_fast[2]; }; -- cgit v1.1 From 6518c0ede9f8b12c7eb4ab5e843bcacb7198652f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: ppc/ppc405: Add update of bi_procfreq field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt the fields offset in the board information for Linux. Since Linux relies on the CPU frequency value, I wonder how it ever worked. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-15-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_uc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'hw') diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 2a1e2d7..ec97b22 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -102,12 +102,13 @@ static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) for (i = 0; i < 32; i++) { stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); } - stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); - stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); + stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); + stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); + stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); for (i = 0; i < 6; i++) { - stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); + stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); } - n = 0x6A; + n = 0x70; /* includes 2 bytes hole */ for (i = 0; i < 6; i++) { stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); } -- cgit v1.1 From 8f2e9d400320d75bb54d693282672cc407d8a128 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: target/ppc: introduce PMUEventType and PMU overflow timers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch starts an IBM Power8+ compatible PMU implementation by adding the representation of PMU events that we are going to sample, PMUEventType. This enum represents a Perf event that is being sampled by a specific counter 'sprn'. Events that aren't available (i.e. no event was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are inactive due to frozen counter bits state are of type 'PMU_EVENT_INACTIVE'. Other types added in this patch are PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added later on. Let's also add the required PMU cycle overflow timers. They will be used to trigger cycle overflows when cycle events are being sampled. This timer will call cpu_ppc_pmu_timer_cb(), which in turn calls fire_PMC_interrupt(). Both functions are stubs that will be implemented later on when EBB support is added. Two new helper files are created to host this new logic. cpu_ppc_pmu_init() will init all overflow timers during CPU init time. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/ppc/spapr_cpu_core.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 58e7341..a57ba70 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -20,6 +20,7 @@ #include "target/ppc/kvm_ppc.h" #include "hw/ppc/ppc.h" #include "target/ppc/mmu-hash64.h" +#include "target/ppc/power8-pmu.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/hw_accel.h" -- cgit v1.1 From 2c4d3a501e55bb90f90577b2e3f0181dc89efd42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Introduce a "chip" property under PHB3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change will help us move the mapping of XSCOM regions under the PHB3 realize routine, which will be necessary for user created PHB3 devices. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-3-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3.c | 1 + hw/ppc/pnv.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a7f9685..3aa42ef 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1092,6 +1092,7 @@ static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, static Property pnv_phb3_properties[] = { DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), + DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 44ae41a..3e43c53 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1231,6 +1231,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, &error_fatal); + object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), + &error_fatal); if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } -- cgit v1.1 From a8fa95c7e621d3cd0dddb653b4f894fac65dec19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Use the chip class to check the index of PHB3 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The maximum number of PHB3 devices per chip can be different depending on the POWER8 processor model. Signed-off-by: Cédric Le Goater Reviewed-by: Daniel Henrique Barboza Message-Id: <20211213132830.108372-4-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 3aa42ef..9c4451c 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -993,7 +993,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; - if (phb->phb_id >= PNV8_CHIP_PHB3_MAX) { + if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { error_setg(errp, "invalid PHB index: %d", phb->phb_id); return; } -- cgit v1.1 From 9e59b09ccf7c3cb0ac666a63f4883f1389b68465 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Drop the "num-phbs" property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is never used. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-5-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 1 - 1 file changed, 1 deletion(-) (limited to 'hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3e43c53..bbebd21 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1771,7 +1771,6 @@ static Property pnv_chip_properties[] = { DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), - DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), DEFINE_PROP_END_OF_LIST(), }; -- cgit v1.1 From 10841a76eb8900ab5718fe91beb6f73ec365291a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change will help us providing support for user created PHB3 devices. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-6-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3_pbcq.c | 11 +++++++++++ hw/ppc/pnv.c | 12 ------------ 2 files changed, 11 insertions(+), 12 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c index a0526aa..c7426cd 100644 --- a/hw/pci-host/pnv_phb3_pbcq.c +++ b/hw/pci-host/pnv_phb3_pbcq.c @@ -284,6 +284,17 @@ static void pnv_pbcq_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev), &pnv_pbcq_spci_xscom_ops, pbcq, name, PNV_XSCOM_PBCQ_SPCI_SIZE); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_nest_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_pci_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, + &pbcq->xscom_spci_regs); } static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index bbebd21..c97fe77 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1226,7 +1226,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) /* PHB3 controllers */ for (i = 0; i < chip->num_phbs; i++) { PnvPHB3 *phb = &chip8->phbs[i]; - PnvPBCQState *pbcq = &phb->pbcq; object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, @@ -1236,17 +1235,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_nest_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_pci_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, - &pbcq->xscom_spci_regs); } } -- cgit v1.1 From 2ff73dda02d8a467ab56a0e497df7888a15af0c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Use QOM hierarchy to scan PHB3 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When -nodefaults is supported for PHB3 devices, the phbs array under the chip will be empty. This will break the XICSFabric handlers, and all interrupt delivery, and the 'info pic' HMP command. Do a QOM loop on the chip children and look for PHB3 devices instead. Signed-off-by: Cédric Le Goater Reviewed-by: Daniel Henrique Barboza Message-Id: <20211213132830.108372-7-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 72 +++++++++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 54 insertions(+), 18 deletions(-) (limited to 'hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c97fe77..e75fc99 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -638,16 +638,25 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); } +static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) +{ + Monitor *mon = opaque; + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + pnv_phb3_msi_pic_print_info(&phb3->msis, mon); + ics_pic_print_info(&phb3->lsis, mon); + } + return 0; +} + static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) { Pnv8Chip *chip8 = PNV8_CHIP(chip); - int i; ics_pic_print_info(&chip8->psi.ics, mon); - for (i = 0; i < chip->num_phbs; i++) { - pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); - ics_pic_print_info(&chip8->phbs[i].lsis, mon); - } + object_child_foreach(OBJECT(chip), + pnv_chip_power8_pic_print_info_child, mon); } static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) @@ -1789,10 +1798,32 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) return NULL; } +typedef struct ForeachPhb3Args { + int irq; + ICSState *ics; +} ForeachPhb3Args; + +static int pnv_ics_get_child(Object *child, void *opaque) +{ + ForeachPhb3Args *args = opaque; + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + if (ics_valid_irq(&phb3->lsis, args->irq)) { + args->ics = &phb3->lsis; + } + if (ics_valid_irq(ICS(&phb3->msis), args->irq)) { + args->ics = ICS(&phb3->msis); + } + } + return args->ics ? 1 : 0; +} + static ICSState *pnv_ics_get(XICSFabric *xi, int irq) { PnvMachineState *pnv = PNV_MACHINE(xi); - int i, j; + ForeachPhb3Args args = { irq, NULL }; + int i; for (i = 0; i < pnv->num_chips; i++) { PnvChip *chip = pnv->chips[i]; @@ -1801,32 +1832,37 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) if (ics_valid_irq(&chip8->psi.ics, irq)) { return &chip8->psi.ics; } - for (j = 0; j < chip->num_phbs; j++) { - if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { - return &chip8->phbs[j].lsis; - } - if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { - return ICS(&chip8->phbs[j].msis); - } + + object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args); + if (args.ics) { + return args.ics; } } return NULL; } +static int pnv_ics_resend_child(Object *child, void *opaque) +{ + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + ics_resend(&phb3->lsis); + ics_resend(ICS(&phb3->msis)); + } + return 0; +} + static void pnv_ics_resend(XICSFabric *xi) { PnvMachineState *pnv = PNV_MACHINE(xi); - int i, j; + int i; for (i = 0; i < pnv->num_chips; i++) { PnvChip *chip = pnv->chips[i]; Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); ics_resend(&chip8->psi.ics); - for (j = 0; j < chip->num_phbs; j++) { - ics_resend(&chip8->phbs[j].lsis); - ics_resend(ICS(&chip8->phbs[j].msis)); - } + object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL); } } -- cgit v1.1 From 422fd92e613ab6b5239538bf2dc1202eb9d3f0f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and each PEC can have several PHBs : * PEC0 provides 1 PHB (PHB0) * PEC1 provides 2 PHBs (PHB1 and PHB2) * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5) A num_pecs class attribute represents better the logic units of the POWER9 chip. Use that instead of num_phbs which fits POWER8 chips. This will ease adding support for user created devices. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-8-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e75fc99..2fc2b0d 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -667,7 +667,7 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) pnv_xive_pic_print_info(&chip9->xive, mon); pnv_psi_pic_print_info(&chip9->psi, mon); - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; for (j = 0; j < pec->num_stacks; j++) { pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); @@ -1344,15 +1344,13 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + /* Number of PECs is the chip default */ + chip->num_pecs = pcc->num_pecs; + + for (i = 0; i < chip->num_pecs; i++) { object_initialize_child(obj, "pec[*]", &chip9->pecs[i], TYPE_PNV_PHB4_PEC); } - - /* - * Number of PHBs is the chip default - */ - chip->num_phbs = pcc->num_phbs; } static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) @@ -1388,7 +1386,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) int i, j; int phb_id = 0; - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); uint32_t pec_nest_base; @@ -1416,8 +1414,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); - for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; - j++, phb_id++) { + for (j = 0; j < pec->num_stacks; j++, phb_id++) { PnvPhb4PecStack *stack = &pec->stacks[j]; Object *obj = OBJECT(&stack->phb); @@ -1573,7 +1570,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->xscom_core_base = pnv_chip_power9_xscom_core_base; k->xscom_pcba = pnv_chip_power9_xscom_pcba; dc->desc = "PowerNV Chip POWER9"; - k->num_phbs = 6; + k->num_pecs = PNV9_CHIP_MAX_PEC; device_class_set_parent_realize(dc, pnv_chip_power9_realize, &k->parent_realize); -- cgit v1.1 From 12060cbd3fd42e2a263c473829f5872c89dc71d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Introduce version and device_id class atributes for PHB4 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It prepares ground for PHB5 which has different values. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-9-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 2 ++ hw/ppc/pnv.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 741ddc9..9f72272 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -499,6 +499,8 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->compat_size = sizeof(compat); pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); + pecc->version = PNV_PHB4_VERSION; + pecc->device_id = PNV_PHB4_DEVICE_ID; } static const TypeInfo pnv_pec_type_info = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 2fc2b0d..78436a3 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1421,9 +1421,9 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) object_property_set_int(obj, "index", phb_id, &error_fatal); object_property_set_int(obj, "chip-id", chip->chip_id, &error_fatal); - object_property_set_int(obj, "version", PNV_PHB4_VERSION, + object_property_set_int(obj, "version", pecc->version, &error_fatal); - object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, + object_property_set_int(obj, "device-id", pecc->device_id, &error_fatal); object_property_set_link(obj, "stack", OBJECT(stack), &error_abort); -- cgit v1.1 From 6f43d2551fba2569e67c8c1ac4e8768a566738eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Introduce a "chip" property under the PHB4 model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit And check the PEC index using the chip class. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-10-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 7 +++++++ hw/ppc/pnv.c | 2 ++ 2 files changed, 9 insertions(+) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 9f72272..4b32b5a 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -382,6 +382,11 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) assert(pec->system_memory); + if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { + error_setg(errp, "invalid PEC index: %d", pec->index); + return; + } + /* Create stacks */ for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; @@ -462,6 +467,8 @@ static Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), DEFINE_PROP_UINT32("num-stacks", PnvPhb4PecState, num_stacks, 0), DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), + DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, + PnvChip *), DEFINE_PROP_LINK("system-memory", PnvPhb4PecState, system_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 78436a3..ceee63c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1402,6 +1402,8 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) &error_fatal); object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, &error_fatal); + object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), + &error_fatal); object_property_set_link(OBJECT(pec), "system-memory", OBJECT(get_system_memory()), &error_abort); if (!qdev_realize(DEVICE(pec), NULL, errp)) { -- cgit v1.1 From cf0ee6955cc2f7f256e44c4f8198f69aae6ea39c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Introduce a num_stack class attribute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Each PEC device of the POWER9 chip has a predefined number of stacks, equivalent of a root port complex: PEC0 -> 1 stack PEC1 -> 2 stacks PEC2 -> 3 stacks Introduce a class attribute to hold these values and remove the "num-stacks" property. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-11-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 12 +++++++++++- hw/ppc/pnv.c | 7 ------- 2 files changed, 11 insertions(+), 8 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 4b32b5a..293909b 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -377,6 +377,7 @@ static void pnv_pec_instance_init(Object *obj) static void pnv_pec_realize(DeviceState *dev, Error **errp) { PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); char name[64]; int i; @@ -387,6 +388,8 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) return; } + pec->num_stacks = pecc->num_stacks[pec->index]; + /* Create stacks */ for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; @@ -465,7 +468,6 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, static Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), - DEFINE_PROP_UINT32("num-stacks", PnvPhb4PecState, num_stacks, 0), DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, PnvChip *), @@ -484,6 +486,13 @@ static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; } +/* + * PEC0 -> 1 stack + * PEC1 -> 2 stacks + * PEC2 -> 3 stacks + */ +static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 }; + static void pnv_pec_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -508,6 +517,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->stk_compat_size = sizeof(stk_compat); pecc->version = PNV_PHB4_VERSION; pecc->device_id = PNV_PHB4_DEVICE_ID; + pecc->num_stacks = pnv_pec_num_stacks; } static const TypeInfo pnv_pec_type_info = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ceee63c..3957a8c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1393,13 +1393,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) uint32_t pec_pci_base; object_property_set_int(OBJECT(pec), "index", i, &error_fatal); - /* - * PEC0 -> 1 stack - * PEC1 -> 2 stacks - * PEC2 -> 3 stacks - */ - object_property_set_int(OBJECT(pec), "num-stacks", i + 1, - &error_fatal); object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, &error_fatal); object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), -- cgit v1.1 From aa8cc84d88945088e4588aeaa31573fb4ed3b27a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Compute the PHB index from the PHB4 PEC model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the num_stacks class attribute to compute the PHB index depending on the PEC index : * PEC0 provides 1 PHB (PHB0) * PEC1 provides 2 PHBs (PHB1 and PHB2) * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5) The routine pnv_pec_phb_offset() is a bit complex but it also prepares ground for PHB5 which has a different layout of stacks: 3 per PECs. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-12-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 16 ++++++++++++++++ hw/ppc/pnv.c | 4 +--- 2 files changed, 17 insertions(+), 3 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 293909b..a7dd417 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -374,6 +374,19 @@ static void pnv_pec_instance_init(Object *obj) } } +static int pnv_pec_phb_offset(PnvPhb4PecState *pec) +{ + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + int index = pec->index; + int offset = 0; + + while (index--) { + offset += pecc->num_stacks[index]; + } + + return offset; +} + static void pnv_pec_realize(DeviceState *dev, Error **errp) { PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); @@ -394,8 +407,10 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; Object *stk_obj = OBJECT(stack); + int phb_id = pnv_pec_phb_offset(pec) + i; object_property_set_int(stk_obj, "stack-no", i, &error_abort); + object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort); object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort); if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) { return; @@ -538,6 +553,7 @@ static void pnv_pec_stk_instance_init(Object *obj) PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj); object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); + object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index"); } static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3957a8c..7122002 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1384,7 +1384,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) { Pnv9Chip *chip9 = PNV9_CHIP(chip); int i, j; - int phb_id = 0; for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; @@ -1409,11 +1408,10 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); - for (j = 0; j < pec->num_stacks; j++, phb_id++) { + for (j = 0; j < pec->num_stacks; j++) { PnvPhb4PecStack *stack = &pec->stacks[j]; Object *obj = OBJECT(&stack->phb); - object_property_set_int(obj, "index", phb_id, &error_fatal); object_property_set_int(obj, "chip-id", chip->chip_id, &error_fatal); object_property_set_int(obj, "version", pecc->version, -- cgit v1.1 From 8da4f8f7b7e7ab896834130a139528e4b1c0b446 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Remove "system-memory" property from PHB4 PEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is not useful and will be in the way for support of user created PHB4 devices. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-13-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 6 +----- hw/ppc/pnv.c | 2 -- 2 files changed, 1 insertion(+), 7 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index a7dd417..dfed2af 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -124,7 +124,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) { PnvPhb4PecState *pec = stack->pec; - MemoryRegion *sysmem = pec->system_memory; + MemoryRegion *sysmem = get_system_memory(); uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN]; uint64_t bar, mask, size; char name[64]; @@ -394,8 +394,6 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) char name[64]; int i; - assert(pec->system_memory); - if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { error_setg(errp, "invalid PEC index: %d", pec->index); return; @@ -486,8 +484,6 @@ static Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_LINK("system-memory", PnvPhb4PecState, system_memory, - TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7122002..57a5180 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1396,8 +1396,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) &error_fatal); object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), &error_fatal); - object_property_set_link(OBJECT(pec), "system-memory", - OBJECT(get_system_memory()), &error_abort); if (!qdev_realize(DEVICE(pec), NULL, errp)) { return; } -- cgit v1.1 From 13480fc58a57e5274894cdb87120fd49c9c95ddc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Move realize of PEC stacks under the PEC model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change will help us providing support for user created PHB4 devices. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-14-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 34 ++++++++++++++++++++++++++++++---- hw/ppc/pnv.c | 37 ++++--------------------------------- 2 files changed, 34 insertions(+), 37 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index dfed2af..24a3adc 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -556,6 +556,10 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) { PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec = stack->pec; + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + PnvChip *chip = pec->chip; + uint32_t pec_nest_base; + uint32_t pec_pci_base; char name[64]; assert(pec); @@ -579,10 +583,32 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb), &pnv_phb4_xscom_ops, &stack->phb, name, 0x40); - /* - * Let the machine/chip realize the PHB object to customize more - * easily some fields - */ + object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, + &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, + &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "device-id", pecc->device_id, + &error_fatal); + object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { + return; + } + + pec_nest_base = pecc->xscom_nest_base(pec); + pec_pci_base = pecc->xscom_pci_base(pec); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(chip, + pec_nest_base + 0x40 * (stack->stack_no + 1), + &stack->nest_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + 0x40 * (stack->stack_no + 1), + &stack->pci_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + + 0x40 * stack->stack_no, + &stack->phb_regs_mr); } static Property pnv_pec_stk_properties[] = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 57a5180..c0b47a7 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1380,10 +1380,10 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) } } -static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) +static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) { Pnv9Chip *chip9 = PNV9_CHIP(chip); - int i, j; + int i; for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; @@ -1405,35 +1405,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); - - for (j = 0; j < pec->num_stacks; j++) { - PnvPhb4PecStack *stack = &pec->stacks[j]; - Object *obj = OBJECT(&stack->phb); - - object_property_set_int(obj, "chip-id", chip->chip_id, - &error_fatal); - object_property_set_int(obj, "version", pecc->version, - &error_fatal); - object_property_set_int(obj, "device-id", pecc->device_id, - &error_fatal); - object_property_set_link(obj, "stack", OBJECT(stack), - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { - return; - } - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - pec_nest_base + 0x40 * (stack->stack_no + 1), - &stack->nest_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + 0x40 * (stack->stack_no + 1), - &stack->pci_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + - 0x40 * stack->stack_no, - &stack->phb_regs_mr); - } } } @@ -1529,8 +1500,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), &chip9->homer.regs); - /* PHBs */ - pnv_chip_power9_phb_realize(chip, &local_err); + /* PEC PHBs */ + pnv_chip_power9_pec_realize(chip, &local_err); if (local_err) { error_propagate(errp, local_err); return; -- cgit v1.1 From 0e6232bc3cb96bdf6fac1b5d7659aa9887afe657 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When -nodefaults is supported for PHB4 devices, the pecs array under the chip will be empty. This will break the 'info pic' HMP command. Do a QOM loop on the chip children and look for PEC PHB4 devices instead. Signed-off-by: Cédric Le Goater Reviewed-by: Daniel Henrique Barboza Message-Id: <20211213132830.108372-15-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c0b47a7..29ee0d0 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -659,20 +659,26 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) pnv_chip_power8_pic_print_info_child, mon); } +static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) +{ + Monitor *mon = opaque; + PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); + + if (phb4) { + pnv_phb4_pic_print_info(phb4, mon); + } + return 0; +} + static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) { Pnv9Chip *chip9 = PNV9_CHIP(chip); - int i, j; pnv_xive_pic_print_info(&chip9->xive, mon); pnv_psi_pic_print_info(&chip9->psi, mon); - for (i = 0; i < chip->num_pecs; i++) { - PnvPhb4PecState *pec = &chip9->pecs[i]; - for (j = 0; j < pec->num_stacks; j++) { - pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); - } - } + object_child_foreach_recursive(OBJECT(chip), + pnv_chip_power9_pic_print_info_child, mon); } static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, -- cgit v1.1