From 0f2bf05ce7b2b64f2a3ecb98de10a8100228c9a6 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 31 Oct 2017 11:50:51 +0000 Subject: xlnx-zcu102: Specify the max number of CPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specify the number of CPUs that can run on ZynqMP. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..e2d15a1 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -240,6 +240,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; + mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; } static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { -- cgit v1.1 From cda607d5e0178d0268066d94dd06b89614304a7d Mon Sep 17 00:00:00 2001 From: Subbaraya Sundeep Date: Tue, 31 Oct 2017 11:50:51 +0000 Subject: msf2: Remove dead code reported by Coverity Fixed incorrect frame size mask, validated maximum frame size in spi_write and removed dead code. Signed-off-by: Subbaraya Sundeep Reviewed-by: Darren Kenny Reviewed-by: Alistair Francis Message-id: 1508898544-10307-1-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/mss-spi.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'hw') diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c index 5a8e308..d60daba 100644 --- a/hw/ssi/mss-spi.c +++ b/hw/ssi/mss-spi.c @@ -76,9 +76,10 @@ #define C_BIGFIFO (1 << 29) #define C_RESET (1 << 31) -#define FRAMESZ_MASK 0x1F +#define FRAMESZ_MASK 0x3F #define FMCOUNT_MASK 0x00FFFF00 #define FMCOUNT_SHIFT 8 +#define FRAMESZ_MAX 32 static void txfifo_reset(MSSSpiState *s) { @@ -104,10 +105,8 @@ static void set_fifodepth(MSSSpiState *s) s->fifo_depth = 32; } else if (size <= 16) { s->fifo_depth = 16; - } else if (size <= 32) { - s->fifo_depth = 8; } else { - s->fifo_depth = 4; + s->fifo_depth = 8; } } @@ -301,6 +300,17 @@ static void spi_write(void *opaque, hwaddr addr, if (s->enabled) { break; } + /* + * [31:6] bits are reserved bits and for future use. + * [5:0] are for frame size. Only [5:0] bits are validated + * during write, [31:6] bits are untouched. + */ + if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided." + "Maximum frame size is %u\n", + __func__, value & FRAMESZ_MASK, FRAMESZ_MAX); + break; + } s->regs[R_SPI_DFSIZE] = value; break; -- cgit v1.1 From db7b98c6bb57312a49d9c47ee890e5e50a1db86d Mon Sep 17 00:00:00 2001 From: Subbaraya Sundeep Date: Tue, 31 Oct 2017 11:50:52 +0000 Subject: msf2: Wire up SYSRESETREQ in SoC for system reset Implemented system reset by creating SYSRESETREQ gpio out from nvic. Signed-off-by: Subbaraya Sundeep Message-id: 1509253165-7434-1-git-send-email-sundeep.lkml@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/msf2-soc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'hw') diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 6f97fa9..a8ec2cd 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -57,6 +57,13 @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; +static void do_sys_reset(void *opaque, int n, int level) +{ + if (level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + static void m2sxxx_soc_initfn(Object *obj) { MSF2State *s = MSF2_SOC(obj); @@ -125,6 +132,10 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) error_append_hint(errp, "m3clk can not be zero\n"); return; } + + qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, + qemu_allocate_irq(&do_sys_reset, NULL, 0)); + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; for (i = 0; i < MSF2_NUM_UARTS; i++) { -- cgit v1.1 From 168df2dea701bbf3118bdfea7794369dfa694d3d Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Tue, 31 Oct 2017 11:50:52 +0000 Subject: hw/pci-host/gpex: Improve INTX to gsi routing error checking We exposed gpex_set_irq_num() for machines to set the INTx to GSI routing. However if the machine forgets to call that function we currently do not check the association was properly done. Let's initialize gsi values to -1 and if this value is found in gpex_route_intx_pin_to_irq, set the routing mode as disabled. Signed-off-by: Eric Auger Message-id: 1508776211-22175-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pci-host/gpex.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 4090793..edf305b 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -57,9 +57,14 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) { PCIINTxRoute route; GPEXHost *s = opaque; + int gsi = s->irq_num[pin]; - route.mode = PCI_INTX_ENABLED; - route.irq = s->irq_num[pin]; + route.irq = gsi; + if (gsi < 0) { + route.mode = PCI_INTX_DISABLED; + } else { + route.mode = PCI_INTX_ENABLED; + } return route; } @@ -81,6 +86,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->io_ioport); for (i = 0; i < GPEX_NUM_IRQS; i++) { sysbus_init_irq(sbd, &s->irq[i]); + s->irq_num[i] = -1; } pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq, -- cgit v1.1