From 9925c8bb81d34339ea0433192fdb1d58c12b8edb Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 22 Oct 2021 16:01:29 +1000 Subject: hw/riscv: virt: Don't use a macro for the PLIC configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using a macro for the PLIC configuration doesn't make the code any easier to read. Instead it makes it harder to figure out what is going on, so let's remove it. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b3b431c..28a5909 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -758,7 +758,7 @@ static char *plic_hart_config_string(int hart_count) int i; for (i = 0; i < hart_count; i++) { - vals[i] = VIRT_PLIC_HART_CONFIG; + vals[i] = "MS"; } vals[i] = NULL; -- cgit v1.1 From bf357e1d72cd8b7b590518dacdf4b65beb2c61e2 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 22 Oct 2021 16:01:30 +1000 Subject: hw/riscv: boot: Add a PLIC config string function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a generic function that can create the PLIC strings. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com --- hw/riscv/boot.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'hw') diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d1ffc7b..519fa45 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -38,6 +38,31 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) return harts->harts[0].env.misa_mxl_max == MXL_RV32; } +/* + * Return the per-socket PLIC hart topology configuration string + * (caller must free with g_free()) + */ +char *riscv_plic_hart_config_string(int hart_count) +{ + g_autofree const char **vals = g_new(const char *, hart_count + 1); + int i; + + for (i = 0; i < hart_count; i++) { + CPUState *cs = qemu_get_cpu(i); + CPURISCVState *env = &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVS)) { + vals[i] = "MS"; + } else { + vals[i] = "M"; + } + } + vals[i] = NULL; + + /* g_strjoinv() obliges us to cast away const here */ + return g_strjoinv(",", (char **)vals); +} + target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr) { if (riscv_is_32bit(harts)) { -- cgit v1.1 From 4e8fb53c0b58cbb18cd243a5b067e4f26db83f77 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 22 Oct 2021 16:01:31 +1000 Subject: hw/riscv: sifive_u: Use the PLIC config helper function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com --- hw/riscv/sifive_u.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'hw') diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 0217006..589ae72 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -811,7 +811,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) MemoryRegion *mask_rom = g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); char *plic_hart_config; - size_t plic_hart_config_len; int i, j; NICInfo *nd = &nd_table[0]; @@ -852,18 +851,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) l2lim_mem); /* create PLIC hart topology configuration string */ - plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * - ms->smp.cpus; - plic_hart_config = g_malloc0(plic_hart_config_len); - for (i = 0; i < ms->smp.cpus; i++) { - if (i != 0) { - strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, - plic_hart_config_len); - } else { - strncat(plic_hart_config, "M", plic_hart_config_len); - } - plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); - } + plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, -- cgit v1.1 From 8486eb8cdcd336de8ae52d95da45af97f54db63e Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 22 Oct 2021 16:01:32 +1000 Subject: hw/riscv: microchip_pfsoc: Use the PLIC config helper function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com --- hw/riscv/microchip_pfsoc.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'hw') diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 3fc8545..57d779f 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -187,7 +187,6 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) MemoryRegion *envm_data = g_new(MemoryRegion, 1); MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); char *plic_hart_config; - size_t plic_hart_config_len; NICInfo *nd; int i; @@ -262,18 +261,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) l2lim_mem); /* create PLIC hart topology configuration string */ - plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * - ms->smp.cpus; - plic_hart_config = g_malloc0(plic_hart_config_len); - for (i = 0; i < ms->smp.cpus; i++) { - if (i != 0) { - strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, - plic_hart_config_len); - } else { - strncat(plic_hart_config, "M", plic_hart_config_len); - } - plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); - } + plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); /* PLIC */ s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, -- cgit v1.1 From 7d10ff8a4de7a9bff1e7b25011f5eb43f24a6713 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 22 Oct 2021 16:01:33 +1000 Subject: hw/riscv: virt: Use the PLIC config helper function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20211022060133.3045020-5-alistair.francis@opensource.wdc.com --- hw/riscv/virt.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) (limited to 'hw') diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 28a5909..3af0741 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -748,24 +748,6 @@ static FWCfgState *create_fw_cfg(const MachineState *mc) return fw_cfg; } -/* - * Return the per-socket PLIC hart topology configuration string - * (caller must free with g_free()) - */ -static char *plic_hart_config_string(int hart_count) -{ - g_autofree const char **vals = g_new(const char *, hart_count + 1); - int i; - - for (i = 0; i < hart_count; i++) { - vals[i] = "MS"; - } - vals[i] = NULL; - - /* g_strjoinv() obliges us to cast away const here */ - return g_strjoinv(",", (char **)vals); -} - static void virt_machine_init(MachineState *machine) { const MemMapEntry *memmap = virt_memmap; @@ -839,7 +821,7 @@ static void virt_machine_init(MachineState *machine) } /* Per-socket PLIC hart topology configuration string */ - plic_hart_config = plic_hart_config_string(hart_count); + plic_hart_config = riscv_plic_hart_config_string(hart_count); /* Per-socket PLIC */ s->plic[i] = sifive_plic_create( -- cgit v1.1 From 9b144ed444f1fb3149d9ec17f0c4a64d4fd7d662 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 25 Oct 2021 14:06:57 +1000 Subject: hw/riscv: opentitan: Fixup the PLIC context addresses Fixup the PLIC context address to correctly support the threshold and claim register. Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build") Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com --- hw/riscv/opentitan.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 83e1511..c531450 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -161,8 +161,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18); - qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004); - qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4); + qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); + qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { -- cgit v1.1