From 61c56c8c862b8be9cb71faf74fcd990b3624aa41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 14 Mar 2012 01:38:23 +0100 Subject: mips hw/: Don't use CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Scripted conversion: for file in hw/mips_*.[hc]; do sed -i "s/CPUState/CPUMIPSState/g" $file done Signed-off-by: Andreas Färber Acked-by: Anthony Liguori --- hw/mips_cpudevs.h | 4 ++-- hw/mips_fulong2e.c | 10 +++++----- hw/mips_int.c | 6 +++--- hw/mips_jazz.c | 6 +++--- hw/mips_malta.c | 10 +++++----- hw/mips_mipssim.c | 6 +++--- hw/mips_r4k.c | 6 +++--- hw/mips_timer.c | 20 ++++++++++---------- 8 files changed, 34 insertions(+), 34 deletions(-) (limited to 'hw') diff --git a/hw/mips_cpudevs.h b/hw/mips_cpudevs.h index db82b41..6bea24b 100644 --- a/hw/mips_cpudevs.h +++ b/hw/mips_cpudevs.h @@ -7,9 +7,9 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); /* mips_int.c */ -void cpu_mips_irq_init_cpu(CPUState *env); +void cpu_mips_irq_init_cpu(CPUMIPSState *env); /* mips_timer.c */ -void cpu_mips_clock_init(CPUState *); +void cpu_mips_clock_init(CPUMIPSState *); #endif diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c index dae488a..37dc711 100644 --- a/hw/mips_fulong2e.c +++ b/hw/mips_fulong2e.c @@ -102,7 +102,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index, va_end(ap); } -static int64_t load_kernel (CPUState *env) +static int64_t load_kernel (CPUMIPSState *env) { int64_t kernel_entry, kernel_low, kernel_high; int index = 0; @@ -168,7 +168,7 @@ static int64_t load_kernel (CPUState *env) return kernel_entry; } -static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr) +static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr) { uint32_t *p; @@ -198,7 +198,7 @@ static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr) static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUMIPSState *env = opaque; cpu_state_reset(env); /* TODO: 2E reset stuff */ @@ -248,7 +248,7 @@ static void network_init (void) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUMIPSState *env = cpu_single_env; if (env && level) { cpu_exit(env); @@ -272,7 +272,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device, i2c_bus *smbus; int i; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - CPUState *env; + CPUMIPSState *env; /* init CPUs */ if (cpu_model == NULL) { diff --git a/hw/mips_int.c b/hw/mips_int.c index 477f6ab..6423fd0 100644 --- a/hw/mips_int.c +++ b/hw/mips_int.c @@ -26,7 +26,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) { - CPUState *env = (CPUState *)opaque; + CPUMIPSState *env = (CPUMIPSState *)opaque; if (irq < 0 || irq > 7) return; @@ -44,7 +44,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) } } -void cpu_mips_irq_init_cpu(CPUState *env) +void cpu_mips_irq_init_cpu(CPUMIPSState *env) { qemu_irq *qi; int i; @@ -55,7 +55,7 @@ void cpu_mips_irq_init_cpu(CPUState *env) } } -void cpu_mips_soft_irq(CPUState *env, int irq, int level) +void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) { if (irq < 0 || irq > 2) { return; diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index d5f1b34..a6bc7ba 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -50,7 +50,7 @@ enum jazz_model_e static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUMIPSState *env = opaque; cpu_state_reset(env); } @@ -97,7 +97,7 @@ static const MemoryRegionOps dma_dummy_ops = { static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUMIPSState *env = cpu_single_env; if (env && level) { cpu_exit(env); @@ -112,7 +112,7 @@ static void mips_jazz_init(MemoryRegion *address_space, { char *filename; int bios_size, n; - CPUState *env; + CPUMIPSState *env; qemu_irq *rc4030, *i8259; rc4030_dma *dmas; void* rc4030_opaque; diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 3335e11..5e26775 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -500,7 +500,7 @@ static void network_init(void) a3 - RAM size in bytes */ -static void write_bootloader (CPUState *env, uint8_t *base, +static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_entry) { uint32_t *p; @@ -736,7 +736,7 @@ static int64_t load_kernel (void) return kernel_entry; } -static void malta_mips_config(CPUState *env) +static void malta_mips_config(CPUMIPSState *env) { env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC); @@ -744,7 +744,7 @@ static void malta_mips_config(CPUState *env) static void main_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUMIPSState *env = opaque; cpu_state_reset(env); /* The bootloader does not need to be rewritten as it is located in a @@ -759,7 +759,7 @@ static void main_cpu_reset(void *opaque) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUMIPSState *env = cpu_single_env; if (env && level) { cpu_exit(env); @@ -781,7 +781,7 @@ void mips_malta_init (ram_addr_t ram_size, int64_t kernel_entry; PCIBus *pci_bus; ISABus *isa_bus; - CPUState *env; + CPUMIPSState *env; qemu_irq *isa_irq; qemu_irq *cpu_exit_irq; int piix4_devfn; diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c index 1fe4ac5..1ea7b58 100644 --- a/hw/mips_mipssim.c +++ b/hw/mips_mipssim.c @@ -46,7 +46,7 @@ static struct _loaderparams { } loaderparams; typedef struct ResetData { - CPUState *env; + CPUMIPSState *env; uint64_t vector; } ResetData; @@ -105,7 +105,7 @@ static int64_t load_kernel(void) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUState *env = s->env; + CPUMIPSState *env = s->env; cpu_state_reset(env); env->active_tc.PC = s->vector & ~(target_ulong)1; @@ -140,7 +140,7 @@ mips_mipssim_init (ram_addr_t ram_size, MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); - CPUState *env; + CPUMIPSState *env; ResetData *reset_info; int bios_size; diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index 96ad808..e2da49c 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -65,7 +65,7 @@ static const MemoryRegionOps mips_qemu_ops = { }; typedef struct ResetData { - CPUState *env; + CPUMIPSState *env; uint64_t vector; } ResetData; @@ -143,7 +143,7 @@ static int64_t load_kernel(void) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUState *env = s->env; + CPUMIPSState *env = s->env; cpu_state_reset(env); env->active_tc.PC = s->vector; @@ -162,7 +162,7 @@ void mips_r4k_init (ram_addr_t ram_size, MemoryRegion *bios; MemoryRegion *iomem = g_new(MemoryRegion, 1); int bios_size; - CPUState *env; + CPUMIPSState *env; ResetData *reset_info; int i; qemu_irq *i8259; diff --git a/hw/mips_timer.c b/hw/mips_timer.c index cf6ac69..7aa9004 100644 --- a/hw/mips_timer.c +++ b/hw/mips_timer.c @@ -27,7 +27,7 @@ #define TIMER_FREQ 100 * 1000 * 1000 /* XXX: do not use a global */ -uint32_t cpu_mips_get_random (CPUState *env) +uint32_t cpu_mips_get_random (CPUMIPSState *env) { static uint32_t lfsr = 1; static uint32_t prev_idx = 0; @@ -42,7 +42,7 @@ uint32_t cpu_mips_get_random (CPUState *env) } /* MIPS R4K timer */ -static void cpu_mips_timer_update(CPUState *env) +static void cpu_mips_timer_update(CPUMIPSState *env) { uint64_t now, next; uint32_t wait; @@ -55,7 +55,7 @@ static void cpu_mips_timer_update(CPUState *env) } /* Expire the timer. */ -static void cpu_mips_timer_expire(CPUState *env) +static void cpu_mips_timer_expire(CPUMIPSState *env) { cpu_mips_timer_update(env); if (env->insn_flags & ISA_MIPS32R2) { @@ -64,7 +64,7 @@ static void cpu_mips_timer_expire(CPUState *env) qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } -uint32_t cpu_mips_get_count (CPUState *env) +uint32_t cpu_mips_get_count (CPUMIPSState *env) { if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; @@ -83,7 +83,7 @@ uint32_t cpu_mips_get_count (CPUState *env) } } -void cpu_mips_store_count (CPUState *env, uint32_t count) +void cpu_mips_store_count (CPUMIPSState *env, uint32_t count) { if (env->CP0_Cause & (1 << CP0Ca_DC)) env->CP0_Count = count; @@ -97,7 +97,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t count) } } -void cpu_mips_store_compare (CPUState *env, uint32_t value) +void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value) { env->CP0_Compare = value; if (!(env->CP0_Cause & (1 << CP0Ca_DC))) @@ -107,12 +107,12 @@ void cpu_mips_store_compare (CPUState *env, uint32_t value) qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); } -void cpu_mips_start_count(CPUState *env) +void cpu_mips_start_count(CPUMIPSState *env) { cpu_mips_store_count(env, env->CP0_Count); } -void cpu_mips_stop_count(CPUState *env) +void cpu_mips_stop_count(CPUMIPSState *env) { /* Store the current value */ env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock), @@ -121,7 +121,7 @@ void cpu_mips_stop_count(CPUState *env) static void mips_timer_cb (void *opaque) { - CPUState *env; + CPUMIPSState *env; env = opaque; #if 0 @@ -139,7 +139,7 @@ static void mips_timer_cb (void *opaque) env->CP0_Count--; } -void cpu_mips_clock_init (CPUState *env) +void cpu_mips_clock_init (CPUMIPSState *env) { env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env); env->CP0_Compare = 0; -- cgit v1.1