From 507161b5f53ae37e2aeeb99e558485146546331e Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 4 Jun 2025 12:24:42 +0930 Subject: hw/riscv/virt: Use setprop_sized_cells for plic The current device tree property uses two cells for the address (and for the size), but assumes the they are less than 32 bits by hard coding the high cell to zero. Use qemu_fdt_setprop_sized_cells to do the job of splitting the upper and lower 32 bits across cells. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Joel Stanley Message-ID: <20250604025450.85327-7-joel@jms.id.au> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4fd966a..67e60ee 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -493,8 +493,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s, s->soc[socket].num_harts * sizeof(uint32_t) * 4); } - qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", - 0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size); + qemu_fdt_setprop_sized_cells(ms->fdt, plic_name, "reg", + 2, plic_addr, 2, s->memmap[VIRT_PLIC].size); qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); riscv_socket_fdt_write_id(ms, plic_name, socket); -- cgit v1.1