From 4917cf44326a1bda2fd7f27303aff7a25ad86518 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Mon, 27 May 2013 05:17:50 +0200 Subject: cpu: Replace cpu_single_env with CPUState current_cpu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move it to qom/cpu.h. Signed-off-by: Andreas Färber --- hw/alpha/typhoon.c | 16 ++++------------ hw/arm/pxa2xx.c | 3 +-- hw/i386/kvmvapic.c | 6 ++++-- hw/i386/pc.c | 11 ++++++----- hw/intc/arm_gic.c | 3 +-- hw/intc/armv7m_nvic.c | 11 ++++++++--- hw/intc/openpic.c | 7 ++----- hw/mips/mips_fulong2e.c | 6 +++--- hw/mips/mips_jazz.c | 6 +++--- hw/mips/mips_malta.c | 6 +++--- hw/misc/vmport.c | 26 ++++++++++++++++---------- hw/ppc/mpc8544_guts.c | 3 ++- hw/ppc/prep.c | 6 +++--- hw/sparc/sun4m.c | 5 ++--- hw/timer/arm_mptimer.c | 8 +++----- 15 files changed, 61 insertions(+), 62 deletions(-) (limited to 'hw') diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 63cc2cb..1c3ac8e 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -72,9 +72,8 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) { - CPUAlphaState *env = cpu_single_env; + CPUState *cpu = current_cpu; TyphoonState *s = opaque; - CPUState *cpu; uint64_t ret = 0; if (addr & 4) { @@ -95,7 +94,6 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) case 0x0080: /* MISC: Miscellaneous Register. */ - cpu = ENV_GET_CPU(env); ret = s->cchip.misc | (cpu->cpu_index & 3); break; @@ -197,7 +195,6 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cpu = CPU(alpha_env_get_cpu(cpu_single_env)); cpu_unassigned_access(cpu, addr, false, false, 0, size); return -1; } @@ -215,7 +212,6 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size) static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) { TyphoonState *s = opaque; - CPUState *cs; uint64_t ret = 0; if (addr & 4) { @@ -302,8 +298,7 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size) break; default: - cs = CPU(alpha_env_get_cpu(cpu_single_env)); - cpu_unassigned_access(cs, addr, false, false, 0, size); + cpu_unassigned_access(current_cpu, addr, false, false, 0, size); return -1; } @@ -315,7 +310,6 @@ static void cchip_write(void *opaque, hwaddr addr, uint64_t v32, unsigned size) { TyphoonState *s = opaque; - CPUState *cpu_single_cpu = CPU(alpha_env_get_cpu(cpu_single_env)); uint64_t val, oldval, newval; if (addr & 4) { @@ -465,7 +459,7 @@ static void cchip_write(void *opaque, hwaddr addr, break; default: - cpu_unassigned_access(cpu_single_cpu, addr, true, false, 0, size); + cpu_unassigned_access(current_cpu, addr, true, false, 0, size); return; } } @@ -480,7 +474,6 @@ static void pchip_write(void *opaque, hwaddr addr, uint64_t v32, unsigned size) { TyphoonState *s = opaque; - CPUState *cs; uint64_t val, oldval; if (addr & 4) { @@ -582,8 +575,7 @@ static void pchip_write(void *opaque, hwaddr addr, break; default: - cs = CPU(alpha_env_get_cpu(cpu_single_env)); - cpu_unassigned_access(cs, addr, true, false, 0, size); + cpu_unassigned_access(current_cpu, addr, true, false, 0, size); return; } } diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 5a22654..3c520d7 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -301,8 +301,7 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, #endif /* Suspend */ - cpu_interrupt(CPU(arm_env_get_cpu(cpu_single_env)), - CPU_INTERRUPT_HALT); + cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); goto message; diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 9850a85..e13678f 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -624,11 +624,13 @@ static int vapic_prepare(VAPICROMState *s) static void vapic_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { - CPUX86State *env = cpu_single_env; + CPUState *cs = current_cpu; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; hwaddr rom_paddr; VAPICROMState *s = opaque; - cpu_synchronize_state(CPU(x86_env_get_cpu(env))); + cpu_synchronize_state(cs); /* * The VAPIC supports two PIO-based hypercalls, both via port 0x7E. diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e00f9dc..5224256 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -886,8 +886,9 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) DeviceState *cpu_get_current_apic(void) { - if (cpu_single_env) { - return cpu_single_env->apic_state; + if (current_cpu) { + X86CPU *cpu = X86_CPU(current_cpu); + return cpu->env.apic_state; } else { return NULL; } @@ -1176,10 +1177,10 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUX86State *env = cpu_single_env; + CPUState *cpu = current_cpu; - if (env && level) { - cpu_exit(CPU(x86_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index b59df06..237d1d6 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -39,8 +39,7 @@ static const uint8_t gic_id[] = { static inline int gic_get_current_cpu(GICState *s) { if (s->num_cpu > 1) { - CPUState *cpu = ENV_GET_CPU(cpu_single_env); - return cpu->cpu_index; + return current_cpu->cpu_index; } return 0; } diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2a57f77..178344b 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -140,6 +140,7 @@ void armv7m_nvic_complete_irq(void *opaque, int irq) static uint32_t nvic_readl(nvic_state *s, uint32_t offset) { + ARMCPU *cpu; uint32_t val; int irq; @@ -171,7 +172,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) case 0x1c: /* SysTick Calibration Value. */ return 10000; case 0xd00: /* CPUID Base. */ - return cpu_single_env->cp15.c0_cpuid; + cpu = ARM_CPU(current_cpu); + return cpu->env.cp15.c0_cpuid; case 0xd04: /* Interrupt Control State. */ /* VECTACTIVE */ val = s->gic.running_irq[0]; @@ -206,7 +208,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) val |= (1 << 31); return val; case 0xd08: /* Vector Table Offset. */ - return cpu_single_env->v7m.vecbase; + cpu = ARM_CPU(current_cpu); + return cpu->env.v7m.vecbase; case 0xd0c: /* Application Interrupt/Reset Control. */ return 0xfa05000; case 0xd10: /* System Control. */ @@ -279,6 +282,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) { + ARMCPU *cpu; uint32_t oldval; switch (offset) { case 0x10: /* SysTick Control and Status. */ @@ -331,7 +335,8 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) } break; case 0xd08: /* Vector Table Offset. */ - cpu_single_env->v7m.vecbase = value & 0xffffff80; + cpu = ARM_CPU(current_cpu); + cpu->env.v7m.vecbase = value & 0xffffff80; break; case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) == 0x05fa) { diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 937e292..d984dba 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -180,14 +180,11 @@ static int output_to_inttgt(int output) static int get_current_cpu(void) { - CPUState *cpu_single_cpu; - - if (!cpu_single_env) { + if (!current_cpu) { return -1; } - cpu_single_cpu = ENV_GET_CPU(cpu_single_env); - return cpu_single_cpu->cpu_index; + return current_cpu->cpu_index; } static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 03e44d5..9e305d2 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -250,10 +250,10 @@ static void network_init (PCIBus *pci_bus) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUMIPSState *env = cpu_single_env; + CPUState *cpu = current_cpu; - if (env && level) { - cpu_exit(CPU(mips_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 3eac63b..31e138b 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -99,10 +99,10 @@ static const MemoryRegionOps dma_dummy_ops = { static void cpu_request_exit(void *opaque, int irq, int level) { - CPUMIPSState *env = cpu_single_env; + CPUState *cpu = current_cpu; - if (env && level) { - cpu_exit(CPU(mips_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index ceadc72..7e56121 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -770,10 +770,10 @@ static void main_cpu_reset(void *opaque) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUMIPSState *env = cpu_single_env; + CPUState *cpu = current_cpu; - if (env && level) { - cpu_exit(CPU(mips_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } diff --git a/hw/misc/vmport.c b/hw/misc/vmport.c index 7463776..0b5a564 100644 --- a/hw/misc/vmport.c +++ b/hw/misc/vmport.c @@ -62,11 +62,13 @@ static uint64_t vmport_ioport_read(void *opaque, hwaddr addr, unsigned size) { VMPortState *s = opaque; - CPUX86State *env = cpu_single_env; + CPUState *cs = current_cpu; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; unsigned char command; uint32_t eax; - cpu_synchronize_state(CPU(x86_env_get_cpu(env))); + cpu_synchronize_state(cs); eax = env->regs[R_EAX]; if (eax != VMPORT_MAGIC) @@ -89,29 +91,32 @@ static uint64_t vmport_ioport_read(void *opaque, hwaddr addr, static void vmport_ioport_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - CPUX86State *env = cpu_single_env; + X86CPU *cpu = X86_CPU(current_cpu); - env->regs[R_EAX] = vmport_ioport_read(opaque, addr, 4); + cpu->env.regs[R_EAX] = vmport_ioport_read(opaque, addr, 4); } static uint32_t vmport_cmd_get_version(void *opaque, uint32_t addr) { - CPUX86State *env = cpu_single_env; - env->regs[R_EBX] = VMPORT_MAGIC; + X86CPU *cpu = X86_CPU(current_cpu); + + cpu->env.regs[R_EBX] = VMPORT_MAGIC; return 6; } static uint32_t vmport_cmd_ram_size(void *opaque, uint32_t addr) { - CPUX86State *env = cpu_single_env; - env->regs[R_EBX] = 0x1177; + X86CPU *cpu = X86_CPU(current_cpu); + + cpu->env.regs[R_EBX] = 0x1177; return ram_size; } /* vmmouse helpers */ void vmmouse_get_data(uint32_t *data) { - CPUX86State *env = cpu_single_env; + X86CPU *cpu = X86_CPU(current_cpu); + CPUX86State *env = &cpu->env; data[0] = env->regs[R_EAX]; data[1] = env->regs[R_EBX]; data[2] = env->regs[R_ECX]; data[3] = env->regs[R_EDX]; @@ -120,7 +125,8 @@ void vmmouse_get_data(uint32_t *data) void vmmouse_set_data(const uint32_t *data) { - CPUX86State *env = cpu_single_env; + X86CPU *cpu = X86_CPU(current_cpu); + CPUX86State *env = &cpu->env; env->regs[R_EAX] = data[0]; env->regs[R_EBX] = data[1]; env->regs[R_ECX] = data[2]; env->regs[R_EDX] = data[3]; diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index 2e2f2eb..a10abe9 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -68,7 +68,8 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr, unsigned size) { uint32_t value = 0; - CPUPPCState *env = cpu_single_env; + PowerPCCPU *cpu = POWERPC_CPU(current_cpu); + CPUPPCState *env = &cpu->env; addr &= MPC8544_GUTS_MMIO_SIZE - 1; switch (addr) { diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 7b2559d..d07dd01 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -417,10 +417,10 @@ static const MemoryRegionOps PPC_prep_io_ops = { static void cpu_request_exit(void *opaque, int irq, int level) { - CPUPPCState *env = cpu_single_env; + CPUState *cpu = current_cpu; - if (env && level) { - cpu_exit(CPU(ppc_env_get_cpu(env))); + if (cpu && level) { + cpu_exit(cpu); } } diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 90b7b60..7a0c1ab 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -264,9 +264,8 @@ static void secondary_cpu_reset(void *opaque) static void cpu_halt_signal(void *opaque, int irq, int level) { - if (level && cpu_single_env) { - cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)), - CPU_INTERRUPT_HALT); + if (level && current_cpu) { + cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); } } diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index d23462d..fbc69c9 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -49,13 +49,11 @@ typedef struct { static inline int get_current_cpu(ARMMPTimerState *s) { - CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env); - - if (cpu_single_cpu->cpu_index >= s->num_cpu) { + if (current_cpu->cpu_index >= s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", - s->num_cpu, cpu_single_cpu->cpu_index); + s->num_cpu, current_cpu->cpu_index); } - return cpu_single_cpu->cpu_index; + return current_cpu->cpu_index; } static inline void timerblock_update_irq(TimerBlock *tb) -- cgit v1.1