From 39d51eb8bcc603c02342d8f5e1f7a569e5f17e06 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sun, 18 Mar 2007 12:43:40 +0000
Subject: Fix BD flag handling, cause register contents, implement some more
 bits for R2 interrupt handling.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
---
 hw/mips_int.c   | 13 ++++---------
 hw/mips_timer.c |  7 +++++++
 2 files changed, 11 insertions(+), 9 deletions(-)

(limited to 'hw')

diff --git a/hw/mips_int.c b/hw/mips_int.c
index 93d599f..7f9f153 100644
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -20,20 +20,15 @@ void cpu_mips_update_irq(CPUState *env)
 
 void cpu_mips_irq_request(void *opaque, int irq, int level)
 {
-    CPUState *env = first_cpu;
-   
-    uint32_t mask;
+    CPUState *env = (CPUState *)opaque;
 
-    if (irq >= 16)
+    if (irq < 0 || irq > 7)
         return;
 
-    mask = 1 << (irq + CP0Ca_IP);
-
     if (level) {
-        env->CP0_Cause |= mask;
+        env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
     } else {
-        env->CP0_Cause &= ~mask;
+        env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
     }
     cpu_mips_update_irq(env);
 }
-
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index bc83036..055ee5b 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -28,6 +28,9 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count,
     uint64_t now, next;
     uint32_t tmp;
 
+    if (env->CP0_Cause & (1 << CP0Ca_DC))
+        return;
+
     tmp = count;
     if (count == compare)
         tmp++;
@@ -57,6 +60,8 @@ void cpu_mips_store_count (CPUState *env, uint32_t value)
 void cpu_mips_store_compare (CPUState *env, uint32_t value)
 {
     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
+    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
+        env->CP0_Cause &= ~(1 << CP0Ca_TI);
     cpu_mips_irq_request(env, 7, 0);
 }
 
@@ -71,6 +76,8 @@ static void mips_timer_cb (void *opaque)
     }
 #endif
     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
+    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
+        env->CP0_Cause |= 1 << CP0Ca_TI;
     cpu_mips_irq_request(env, 7, 1);
 }
 
-- 
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