From 5c9f43363a84fa13861ebc949ea2453cf7ab4ae3 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Thu, 6 Jun 2013 16:38:03 +0000 Subject: intc/xilinx_intc: Use qemu_set_irq Use qemu_set_irq rather than if-elsing qemu_irq_(lower|raise). No functional change, just reduces verbosity. Cc: qemu-trivial@nongnu.org Signed-off-by: Peter Crosthwaite Signed-off-by: Michael Tokarev --- hw/intc/xilinx_intc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'hw') diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index b106e72..5df7008 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -66,11 +66,7 @@ static void update_irq(struct xlx_pic *p) i = ~0; p->regs[R_IVR] = i; - if ((p->regs[R_MER] & 1) && p->regs[R_IPR]) { - qemu_irq_raise(p->parent_irq); - } else { - qemu_irq_lower(p->parent_irq); - } + qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]); } static uint64_t -- cgit v1.1 From 7f4f0a227fe0b24c35d0898f9ae7d5909fb51137 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 3 Jun 2013 15:12:09 +1000 Subject: char/serial: cosmetic fixes. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some cosmetic fixes to char/serial fixing some checkpatch errors. Cc: qemu-trivial@nongnu.org Signed-off-by: Peter Crosthwaite Reviewed-by: Andreas Färber Signed-off-by: Michael Tokarev --- hw/char/serial.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/char/serial.c b/hw/char/serial.c index 66b6348..bd6813e 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -263,8 +263,9 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) if (s->tsr_retry <= 0) { if (s->fcr & UART_FCR_FE) { s->tsr = fifo_get(s,XMIT_FIFO); - if (!s->xmit_fifo.count) + if (!s->xmit_fifo.count) { s->lsr |= UART_LSR_THRE; + } } else if ((s->lsr & UART_LSR_THRE)) { return FALSE; } else { @@ -461,10 +462,11 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) } else { if(s->fcr & UART_FCR_FE) { ret = fifo_get(s,RECV_FIFO); - if (s->recv_fifo.count == 0) + if (s->recv_fifo.count == 0) { s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); - else + } else { qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); + } s->timeout_ipending = 0; } else { ret = s->rbr; @@ -534,15 +536,21 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) static int serial_can_receive(SerialState *s) { if(s->fcr & UART_FCR_FE) { - if(s->recv_fifo.count < UART_FIFO_LENGTH) - /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is - advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond, - effectively overriding the ITL that the guest has set. */ - return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; - else - return 0; + if (s->recv_fifo.count < UART_FIFO_LENGTH) { + /* + * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 + * if above. If UART_FIFO_LENGTH - fifo.count is advertised the + * effect will be to almost always fill the fifo completely before + * the guest has a chance to respond, effectively overriding the ITL + * that the guest has set. + */ + return (s->recv_fifo.count <= s->recv_fifo.itl) ? + s->recv_fifo.itl - s->recv_fifo.count : 1; + } else { + return 0; + } } else { - return !(s->lsr & UART_LSR_DR); + return !(s->lsr & UART_LSR_DR); } } -- cgit v1.1 From 8e8638fa87ff045f5dadec7342301bf10de776ff Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 3 Jun 2013 15:13:27 +1000 Subject: char/serial: Use generic Fifo8 Use the generic Fifo8 helper provided by QEMU, rather than re-implement privately. Signed-off-by: Peter Crosthwaite Signed-off-by: Michael Tokarev --- hw/char/serial.c | 98 ++++++++++++++++++++------------------------------------ 1 file changed, 34 insertions(+), 64 deletions(-) (limited to 'hw') diff --git a/hw/char/serial.c b/hw/char/serial.c index bd6813e..0a2b6c9 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -92,8 +92,6 @@ #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ #define UART_FCR_FE 0x01 /* FIFO Enable */ -#define XMIT_FIFO 0 -#define RECV_FIFO 1 #define MAX_XMIT_RETRY 4 #ifdef DEBUG_SERIAL @@ -106,50 +104,14 @@ do {} while (0) static void serial_receive1(void *opaque, const uint8_t *buf, int size); -static void fifo_clear(SerialState *s, int fifo) +static inline void recv_fifo_put(SerialState *s, uint8_t chr) { - SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; - memset(f->data, 0, UART_FIFO_LENGTH); - f->count = 0; - f->head = 0; - f->tail = 0; -} - -static int fifo_put(SerialState *s, int fifo, uint8_t chr) -{ - SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; - /* Receive overruns do not overwrite FIFO contents. */ - if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) { - - f->data[f->head++] = chr; - - if (f->head == UART_FIFO_LENGTH) - f->head = 0; - } - - if (f->count < UART_FIFO_LENGTH) - f->count++; - else if (fifo == RECV_FIFO) + if (!fifo8_is_full(&s->recv_fifo)) { + fifo8_push(&s->recv_fifo, chr); + } else { s->lsr |= UART_LSR_OE; - - return 1; -} - -static uint8_t fifo_get(SerialState *s, int fifo) -{ - SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; - uint8_t c; - - if(f->count == 0) - return 0; - - c = f->data[f->tail++]; - if (f->tail == UART_FIFO_LENGTH) - f->tail = 0; - f->count--; - - return c; + } } static void serial_update_irq(SerialState *s) @@ -165,7 +127,7 @@ static void serial_update_irq(SerialState *s) tmp_iir = UART_IIR_CTI; } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && (!(s->fcr & UART_FCR_FE) || - s->recv_fifo.count >= s->recv_fifo.itl)) { + s->recv_fifo.num >= s->recv_fifo_itl)) { tmp_iir = UART_IIR_RDI; } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { tmp_iir = UART_IIR_THRI; @@ -262,8 +224,9 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) if (s->tsr_retry <= 0) { if (s->fcr & UART_FCR_FE) { - s->tsr = fifo_get(s,XMIT_FIFO); - if (!s->xmit_fifo.count) { + s->tsr = fifo8_is_full(&s->xmit_fifo) ? + 0 : fifo8_pop(&s->xmit_fifo); + if (!s->xmit_fifo.num) { s->lsr |= UART_LSR_THRE; } } else if ((s->lsr & UART_LSR_THRE)) { @@ -317,7 +280,11 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, } else { s->thr = (uint8_t) val; if(s->fcr & UART_FCR_FE) { - fifo_put(s, XMIT_FIFO, s->thr); + /* xmit overruns overwrite data, so make space if needed */ + if (fifo8_is_full(&s->xmit_fifo)) { + fifo8_pop(&s->xmit_fifo); + } + fifo8_push(&s->xmit_fifo, s->thr); s->thr_ipending = 0; s->lsr &= ~UART_LSR_TEMT; s->lsr &= ~UART_LSR_THRE; @@ -368,28 +335,28 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, if (val & UART_FCR_RFR) { qemu_del_timer(s->fifo_timeout_timer); s->timeout_ipending=0; - fifo_clear(s,RECV_FIFO); + fifo8_reset(&s->recv_fifo); } if (val & UART_FCR_XFR) { - fifo_clear(s,XMIT_FIFO); + fifo8_reset(&s->xmit_fifo); } if (val & UART_FCR_FE) { s->iir |= UART_IIR_FE; - /* Set RECV_FIFO trigger Level */ + /* Set recv_fifo trigger Level */ switch (val & 0xC0) { case UART_FCR_ITL_1: - s->recv_fifo.itl = 1; + s->recv_fifo_itl = 1; break; case UART_FCR_ITL_2: - s->recv_fifo.itl = 4; + s->recv_fifo_itl = 4; break; case UART_FCR_ITL_3: - s->recv_fifo.itl = 8; + s->recv_fifo_itl = 8; break; case UART_FCR_ITL_4: - s->recv_fifo.itl = 14; + s->recv_fifo_itl = 14; break; } } else @@ -461,8 +428,9 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) ret = s->divider & 0xff; } else { if(s->fcr & UART_FCR_FE) { - ret = fifo_get(s,RECV_FIFO); - if (s->recv_fifo.count == 0) { + ret = fifo8_is_full(&s->recv_fifo) ? + 0 : fifo8_pop(&s->recv_fifo); + if (s->recv_fifo.num == 0) { s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); } else { qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4); @@ -536,7 +504,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) static int serial_can_receive(SerialState *s) { if(s->fcr & UART_FCR_FE) { - if (s->recv_fifo.count < UART_FIFO_LENGTH) { + if (s->recv_fifo.num < UART_FIFO_LENGTH) { /* * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 * if above. If UART_FIFO_LENGTH - fifo.count is advertised the @@ -544,8 +512,8 @@ static int serial_can_receive(SerialState *s) * the guest has a chance to respond, effectively overriding the ITL * that the guest has set. */ - return (s->recv_fifo.count <= s->recv_fifo.itl) ? - s->recv_fifo.itl - s->recv_fifo.count : 1; + return (s->recv_fifo.num <= s->recv_fifo_itl) ? + s->recv_fifo_itl - s->recv_fifo.num : 1; } else { return 0; } @@ -558,7 +526,7 @@ static void serial_receive_break(SerialState *s) { s->rbr = 0; /* When the LSR_DR is set a null byte is pushed into the fifo */ - fifo_put(s, RECV_FIFO, '\0'); + recv_fifo_put(s, '\0'); s->lsr |= UART_LSR_BI | UART_LSR_DR; serial_update_irq(s); } @@ -566,7 +534,7 @@ static void serial_receive_break(SerialState *s) /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ static void fifo_timeout_int (void *opaque) { SerialState *s = opaque; - if (s->recv_fifo.count) { + if (s->recv_fifo.num) { s->timeout_ipending = 1; serial_update_irq(s); } @@ -588,7 +556,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size) if(s->fcr & UART_FCR_FE) { int i; for (i = 0; i < size; i++) { - fifo_put(s, RECV_FIFO, buf[i]); + recv_fifo_put(s, buf[i]); } s->lsr |= UART_LSR_DR; /* call the timeout receive callback in 4 char transmit time */ @@ -668,8 +636,8 @@ static void serial_reset(void *opaque) s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; s->poll_msl = 0; - fifo_clear(s,RECV_FIFO); - fifo_clear(s,XMIT_FIFO); + fifo8_reset(&s->recv_fifo); + fifo8_reset(&s->xmit_fifo); s->last_xmit_ts = qemu_get_clock_ns(vm_clock); @@ -692,6 +660,8 @@ void serial_init_core(SerialState *s) qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, serial_event, s); + fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); + fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); } void serial_exit_core(SerialState *s) -- cgit v1.1 From b5601df7624b461759651c49ac72a189951780b9 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 3 Jun 2013 15:14:48 +1000 Subject: char/serial: serial_ioport_write: Factor out common code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These three lines are common to both FIFO and regular mode. Just factor them out to outside the if rather than replicate the same lines inside both if and else. Cc: qemu-trivial@nongnu.org Signed-off-by: Peter Crosthwaite Reviewed-by: Andreas Färber Signed-off-by: Michael Tokarev --- hw/char/serial.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'hw') diff --git a/hw/char/serial.c b/hw/char/serial.c index 0a2b6c9..017610e 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -285,15 +285,11 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, fifo8_pop(&s->xmit_fifo); } fifo8_push(&s->xmit_fifo, s->thr); - s->thr_ipending = 0; s->lsr &= ~UART_LSR_TEMT; - s->lsr &= ~UART_LSR_THRE; - serial_update_irq(s); - } else { - s->thr_ipending = 0; - s->lsr &= ~UART_LSR_THRE; - serial_update_irq(s); } + s->thr_ipending = 0; + s->lsr &= ~UART_LSR_THRE; + serial_update_irq(s); serial_xmit(NULL, G_IO_OUT, s); } break; -- cgit v1.1 From dcb0780990f7d579b2d6f9c67ef841a75b3a758b Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Mon, 10 Jun 2013 22:24:56 +0200 Subject: hw/scsi: Don't increment a boolean value This fixes a warning from cppcheck. Signed-off-by: Stefan Weil Signed-off-by: Michael Tokarev --- hw/scsi/vmw_pvscsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 48d12f4..446f723 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -389,7 +389,7 @@ pvscsi_process_completion_queue(void *opaque) QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); g_free(pvscsi_req); - has_completed++; + has_completed = true; } if (has_completed) { -- cgit v1.1 From c5633d998a27502ad8cc10c2d46f91b02555ae7a Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Mon, 10 Jun 2013 22:36:22 +0200 Subject: hw/xen: Use g_free instead of free and fix potential memory leaks The wrong functions and the missing calls of g_free were reported by cppcheck. Signed-off-by: Stefan Weil Acked-by: Stefano Stabellini Signed-off-by: Michael Tokarev --- hw/xen/xen_pt_config_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 01872db..8ccc2e4 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -1777,12 +1777,12 @@ static int xen_pt_config_reg_init(XenPCIPassthroughState *s, rc = reg->init(s, reg_entry->reg, reg_grp->base_offset + reg->offset, &data); if (rc < 0) { - free(reg_entry); + g_free(reg_entry); return rc; } if (data == XEN_PT_INVALID_REG) { /* free unused BAR register entry */ - free(reg_entry); + g_free(reg_entry); return 0; } /* set register value */ -- cgit v1.1 From baefb8bf8e4a708c601bbab898a6039cd9cd12e3 Mon Sep 17 00:00:00 2001 From: Stefan Hajnoczi Date: Mon, 3 Jun 2013 10:58:31 +0200 Subject: ivshmem: add missing error exit(2) If the user fails to specify 'chardev' or 'shm' then we cannot continue. Exit right away so that we don't invoke shm_open(3) with a NULL pointer. It would be nice to replace exit(1) with error returns in the PCI device .init() function, but leave that for another patch since exit(1) is currently used elsewhere. Spotted by Coverity. Cc: Cam Macdonell Cc: qemu-stable@nongnu.org Signed-off-by: Stefan Hajnoczi Reviewed-by: Eric Blake Signed-off-by: Michael Tokarev --- hw/misc/ivshmem.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index a19a6d6..5658f73 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -735,6 +735,7 @@ static int pci_ivshmem_init(PCIDevice *dev) if (s->shmobj == NULL) { fprintf(stderr, "Must specify 'chardev' or 'shm' to ivshmem\n"); + exit(1); } IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj); -- cgit v1.1 From ba275adba09adfc0f7ec533f1fddba678d9ba826 Mon Sep 17 00:00:00 2001 From: Hu Tao Date: Fri, 14 Jun 2013 15:11:30 +0800 Subject: piix: fix some printf errors when debug is enabled And use PRIxxx macros if possible. Signed-off-by: Hu Tao Signed-off-by: Michael Tokarev --- hw/acpi/piix4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'hw') diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index e6525ac..756df3b 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -518,7 +518,7 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width) PIIX4PMState *s = opaque; uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr); - PIIX4_DPRINTF("gpe read %x == %x\n", addr, val); + PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val); return val; } @@ -530,7 +530,7 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val, acpi_gpe_ioport_writeb(&s->ar, addr, val); pm_update_sci(s); - PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val); + PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val); } static const MemoryRegionOps piix4_gpe_ops = { @@ -553,15 +553,15 @@ static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) /* Manufacture an "up" value to cause a device check on any hotplug * slot with a device. Extra device checks are harmless. */ val = s->pci0_slot_device_present & s->pci0_hotplug_enable; - PIIX4_DPRINTF("pci_up_read %x\n", val); + PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val); break; case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: val = s->pci0_status.down; - PIIX4_DPRINTF("pci_down_read %x\n", val); + PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val); break; case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: /* No feature defined yet */ - PIIX4_DPRINTF("pci_features_read %x\n", val); + PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val); break; case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: val = s->pci0_hotplug_enable; @@ -579,7 +579,7 @@ static void pci_write(void *opaque, hwaddr addr, uint64_t data, switch (addr) { case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: acpi_piix_eject_slot(opaque, (uint32_t)data); - PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n", + PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, data); break; default: -- cgit v1.1