From 1ed9c8af501f8d1bdf5a8725a038527be059f54d Mon Sep 17 00:00:00 2001 From: David Gibson Date: Fri, 6 Oct 2017 22:21:18 +1100 Subject: target/ppc: Add POWER9 DD2.0 model information At the moment the only POWER9 model which is listed in qemu is v1.0 (aka "DD1"). This is a very early (read, buggy) version which will never be released to the public - it was included in qemu only for the convenience of those doing bringup on the early silicon. For bonus points, we actually had its PVR incorrect in the table (0x004e0000 instead of 0x004e0100). We also never actually implemented the differences in behaviour (read, bugs) that marked DD1 in qemu. Now that we know the PVR for the substantially better v2.0 (DD2) chip, include it and make it the default POWER9 in qemu. For the time being we leave the DD1 definition in place for the poor souls (read, me) who still need to work with DD1 hardware. Signed-off-by: David Gibson --- hw/ppc/spapr_cpu_core.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 3e20b1d..37beb56 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -296,6 +296,7 @@ static const char *spapr_core_models[] = { /* POWER9 */ "power9_v1.0", + "power9_v2.0", }; static Property spapr_cpu_core_properties[] = { -- cgit v1.1