From 06afe2c8840ec39c3b23db0eb830a5f49244b947 Mon Sep 17 00:00:00 2001 From: aurel32 Date: Fri, 22 Aug 2008 08:57:52 +0000 Subject: [sh4] MMU bug fix Some bugs on SH4 MMU are fixed. - When a TLB entry is overwritten or invalidated, tlb_flush_page() should be invoked to invalidate old entry. - When a ASID is changed, tlb_flush() should be invoke to invalidate entries which have old ASID. - The check for shared bit in TLB entry causes multiple TLB hit exception. As SH3's MMU, shared bit is ignored. - ASID is used when MMUCR's SV bit or SR's MD bit is zero. No need to check both bits are zero. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5068 c046a42c-6fe2-441c-8c8c-71466251a162 --- hw/sh7750.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'hw') diff --git a/hw/sh7750.c b/hw/sh7750.c index 0ff3e6d..04a7437 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -30,6 +30,7 @@ #include "sh7750_regs.h" #include "sh7750_regnames.h" #include "sh_intc.h" +#include "exec-all.h" #include "cpu.h" #define NB_DEVICES 4 @@ -356,6 +357,9 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr, s->cpu->mmucr = mem_value; return; case SH7750_PTEH_A7: + /* If asid changes, clear all registered tlb entries. */ + if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) + tlb_flush(s->cpu, 1); s->cpu->pteh = mem_value; return; case SH7750_PTEL_A7: -- cgit v1.1