From c696e1f2b392af19653e82da26df3c61b85ab5a2 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 1 Sep 2020 09:39:02 +0800 Subject: hw/sd: Add Cadence SDHCI emulation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng Acked-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/sd/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'hw/sd/Kconfig') diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig index c5e1e55..633b9af 100644 --- a/hw/sd/Kconfig +++ b/hw/sd/Kconfig @@ -19,3 +19,7 @@ config SDHCI_PCI default y if PCI_DEVICES depends on PCI select SDHCI + +config CADENCE_SDHCI + bool + select SDHCI -- cgit v1.1