From 9a2551ed6f946e96cd54ea3f3499d785a1f27c3d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 5 Sep 2019 08:55:16 -0700 Subject: riscv: sifive_test: Add reset functionality This adds a reset opcode for sifive_test device to trigger a system reset for testing purpose. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_test.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'hw/riscv') diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c index afbb3aa..3557e16 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/riscv/sifive_test.c @@ -22,6 +22,7 @@ #include "hw/hw.h" #include "hw/sysbus.h" #include "qemu/module.h" +#include "sysemu/runstate.h" #include "target/riscv/cpu.h" #include "hw/hw.h" #include "hw/riscv/sifive_test.h" @@ -42,6 +43,9 @@ static void sifive_test_write(void *opaque, hwaddr addr, exit(code); case FINISHER_PASS: exit(0); + case FINISHER_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; default: break; } -- cgit v1.1