From 57a3a6226529e60ef4eb5e11b577f2e532a72acc Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 30 Aug 2021 15:35:15 +1000 Subject: hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com --- hw/riscv/opentitan.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'hw/riscv') diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 048aced..f7cfcf1 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -183,6 +183,9 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_TIMER_TIMEREXPIRED0_0)); + qdev_connect_gpio_out(DEVICE(&s->timer), 0, + qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), + IRQ_M_TIMER)); create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); -- cgit v1.1