From cb3778a0455a2e5a48d7ef0ec8dc656313820389 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 12 Nov 2014 22:44:52 +0100 Subject: PPC: e500 pci host: Add support for ATMUs The e500 PCI controller has configurable windows that allow a guest OS to selectively map parts of the PCI bus space to CPU address space and to selectively map parts of the CPU address space for DMA requests into PCI visible address ranges. So far, we've simply assumed that this mapping is 1:1 and ignored it. However, the PCICSRBAR (CCSR mapped in PCI bus space) always has to live inside the first 32bits of address space. This means if we always treat all mappings as 1:1, this map will collide with our RAM map from the CPU's point of view. So this patch adds proper ATMU support which allows us to keep the PCICSRBAR below 32bits local to the PCI bus and have another, different window to PCI BARs at the upper end of address space. We leverage this on e500plat though, mpc8544ds stays virtually 1:1 like it was before, but now also goes via ATMU. With this patch, I can run guests with lots of RAM and not coincidently access MSI-X mappings while I really want to access RAM. Signed-off-by: Alexander Graf --- hw/ppc/e500.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw/ppc/e500.h') diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index d96f72d..ef224ea 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -19,6 +19,8 @@ typedef struct PPCE500Params { int platform_bus_num_irqs; hwaddr ccsrbar_base; hwaddr pci_pio_base; + hwaddr pci_mmio_base; + hwaddr pci_mmio_bus_base; hwaddr spin_base; } PPCE500Params; -- cgit v1.1